CY7C1021
AC Test Loads and Waveforms
R 481Ω
R 481Ω
ALL INPUT PULSES
90%
10%
5V
5V
OUTPUT
3.0V
GND
90%
10%
OUTPUT
R2
255Ω
R2
255Ω
30 pF
5 pF
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
< 3 ns
< 3 ns
(b)
1021-3
(a)
167
30 pF
1021-4
1.73V
OUTPUT
Equivalent to:
THÉVENIN
EQUIVALENT
Switching Characteristics[5] Over the Operating Range
7C1021-10
7C1021-12
7C1021-15
7C1021-20
Parameter
Description
Min.
Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
Address to Data Valid
10
12
3
15
3
20
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
10
12
15
20
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[6]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
3
10
5
12
6
15
7
20
9
0
3
0
0
3
0
0
3
0
0
3
0
5
5
6
6
7
7
9
9
tPD
10
5
12
6
15
7
20
9
tDBE
tLZBE
tHZBE
0
0
0
0
5
6
7
9
WRITE CYCLE[8]
tWC
tSCE
tAW
Write Cycle Time
10
8
12
9
15
10
10
0
20
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
7
8
tHA
0
0
tSA
0
0
0
0
tPWE
tSD
7
8
10
8
12
10
0
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[6]
5
6
tHD
0
0
0
tLZWE
tHZWE
tBW
3
3
3
3
WE LOW to High Z[6, 7]
5
6
7
9
Byte Enable to End of Write
7
8
9
12
Shaded areas contain preliminary information.
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7.
tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Document #: 38-05054 Rev. **
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