021BV33
CY7C1021BV33
64K x 16 Static RAM
Features
•
3.3V operation (3.0V–3.6V)
•
High speed
—
t
AA
= 10/12/15 ns
•
CMOS for optimum speed/power
•
Low Active Power (L version)
—
576 mW (max.)
•
Low CMOS Standby Power (L version)
—
1.80 mW (max.)
•
Automatic power-down when deselected
•
Independent control of upper and lower bits
•
Available in 44-pin TSOP II and 400-mil SOJ
•
Available in a 48-Ball Mini BGA package
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
1
through I/O
8
), is
written into the location specified on the address pins (A
0
through A
15
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
9
through I/O
16
) is written into the location
specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O
1
to I/O
8
. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O
9
to I/O
16.
See the
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
The input/output pins (I/O
1
through I/O
16
) are placed in a
high-impedance state when the device is deselected
(CE HIGH), the outputs are disabled (OE HIGH), the BHE and
BLE are disabled (BHE, BLE HIGH), or during a write opera-
tion (CE LOW, and WE LOW).
The CY7C1021BV is available in 400-mil-wide SOJ, standard
44-pin TSOP Type II, and 48-ball mini BGA packages.
Functional Description
[1]
The CY7C1021BV is a high-performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an au-
tomatic power-down feature that significantly reduces power
consumption when deselected.
Logic Block Diagram
DATA IN DRIVERS
Pin Configurations
SOJ / TSOP II
Top View
A
4
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
V
CC
V
SS
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
64K x 16
RAM Array
512 X 2048
I/O
1
–I/O
8
I/O
9
–I/O
16
COLUMN DECODER
BHE
WE
CE
OE
BLE
A5
A6
A7
OE
BHE
BLE
I/O16
I/O15
I/O14
I/O13
V
SS
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
NC
ROW DECODER
Selection Guide
7C1021BV-8
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current
(mA)
Commercial
Industrial
Commercial
L
8
170
190
5
0.500
7C1021BV-10
10
160
180
5
0.500
7C1021BV-12
12
150
170
5
0.500
7C1021BV-15
15
140
160
5
0.500
Shaded areas contain advance information.
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05148 Rev. *A
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
•
SENSE AMPS
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 13, 2002
CYPRESS [ CYPRESS SEMICONDUCTOR ]
