CY7C1041D-10ZSXI 参数 Datasheet PDF下载

CY7C1041D

Switching Waveforms

(continued)

Read Cycle No. 2 (OE Controlled)

[15,16]

ADDRESS

t

RC

CE

t

ACE

OE

BHE, BLE

t

DOE

t

LZOE

t

DBE

t

LZBE

DATA OUT

V

CC

SUPPLY

CURRENT

HIGH IMPEDANCE

t

LZCE

t

PU

50%

DATA VALID

t

PD

50%

ISB

t

HZCE

t

HZBE

t

HZOE

HIGH

IMPEDANCE

ICC

Write Cycle No. 1 (CE Controlled)

[17, 18]

t

WC

ADDRESS

CE

t

SA

t

SCE

t

AW

t

PWE

WE

t

BW

BHE, BLE

t

SD

DATAI/O

t

HD

t

HA

Notes:

15. WE is HIGH for read cycle.

16. Address valid prior to or coincident with CE transition LOW

17. Data I/O is high impedance if OE or BHE and/or BLE= V

IH

.

18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.

Document #: 38-05472 Rev. *C

Page 5 of 9