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CY7C1338B-100AC 参数 Datasheet PDF下载

CY7C1338B-100AC图片预览
型号: CY7C1338B-100AC
PDF下载: 下载PDF文件 查看货源
内容描述: 128K ×32的同步,流通型3.3V高速缓存RAM [128K x 32 Synchronous-Flow-Through 3.3V Cache RAM]
分类和应用: 存储内存集成电路静态存储器时钟
文件页数/大小: 18 页 / 600 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY7C1338B
Cycle Description Table
[1, 2, 3]
Cycle Description
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Snooze Mode, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
ADD
Used
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CE
1
H
L
L
L
X
X
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
CE
3
X
X
H
X
X
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
CE
2
X
L
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
ZZ
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ADSP
X
L
L
H
H
X
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
ADSC
L
X
X
L
L
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
ADV
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
WE
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
OE
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
CLK
DQ
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
X
High-Z
L-H Q
L-H High-Z
L-H D
L-H Q
L-H High-Z
L-H Q
L-H High-Z
L-H Q
L-H High-Z
L-H D
L-H D
L-H Q
L-H High-Z
L-H Q
L-H High-Z
L-H D
L-H D
Notes:
1. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW.
2. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWS
[3:0].
Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE
is a “Don't Care” for the remainder of the write cycle.
3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ = High-Z when OE is inactive, and DQ = data when OE is active.
Document #: 38-05143 Rev. **
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