CY7C185
Switching Waveforms
Read Cycle No.1[10,11]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No.2[12,13]
t
RC
CE
1
CE
2
t
ACE
OOEE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
ICC
ISB
V
CC
SUPPLY
CURRENT
50%
50%
[11,13]
Write Cycle No. 1 (WE Controlled)
t
WC
ADDRESS
t
CE
1
SCEI
t
t
HA
AW
t
CE
CE
SCE2
2
t
SA
t
PWE
WE
OE
t
SD
t
HD
DATA VALID
NOTE 14
t
IN
DATA I/O
HZOE
10. Device is continuously selected. OE, CE1 = VIL. CE2 = VIH
.
11. WE is HIGH for read cycle.
12. Data I/O is High Z if OE = VIH, CE1 = VIH, WE = VIL, or CE2=VIL
.
13. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. CE1 and WE must be LOW and CE2 must be HIGH
to initiate write. A write can be terminated by CE1 or WE going HIGH or CE2 going LOW. The data input set-up and hold timing should be referenced to the
rising edge of the signal that terminates the write.
14. During this period, the I/Os are in the output state and input signals should not be applied.
Document #: 38-05043 Rev. *A
Page 5 of 11
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