CY7C4425/4205/4215
CY7C4225/4235/4245
Logic Block Diagram
D
0 – 17
INPUT
REGISTER
WCLK
WEN
WRITE
CONTROL
DUAL PORT
RAM ARRAY
64 x 18
256 x 18
512 x 18
1K x 18
2K x 18
4K x 18
FLAG
PROGRAM
REGISTER
FLAG
LOGIC
FF
EF
PAE
PAF
SMODE
WRITE
POINTER
READ
POINTER
RS
RESET
LOGIC
FL/RT
WXI
WXO/HF
RXI
RXO
EXPANSION
LOGIC
THREE–STATE
OUTPUT REGISTER
READ
CONTROL
OE
42X5–1
Q
0 – 17
RCLK
REN
Pin Configurations
REN
LD
OE
RS
V
CC
GND
EF
Q
17
Q
16
GND
Q
15
V
CC
/SMODE
PLCC
Top View
RCLK
REN
LD
OE
RS
GND
GND
GND
Q
15
V
CC
V
CC
Q
17
D
16
D
17
GND
RCLK
TQFP
Top View
9 8 7
D
14
D
13
D
12
D
11
D
10
D
9
V
CC
D
8
GND
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
6 5
4
3
2 1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
CC
/SMODE
Q
14
Q
13
GND
Q
12
Q
11
V
CC
Q
10
Q
9
GND
Q
8
Q
7
V
CC
Q
6
Q
5
GND
Q
4
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q
14
Q
13
GND
Q
12
Q
11
V
CC
Q
10
Q
9
GND
Q
8
Q
7
Q
6
Q
5
GND
Q
4
V
CC
Q
16
D
15
D
16
D
17
EF
CY7C4425
CY7C4205
CY7C4215
CY7C4225
CY7C4235
CY7C4245
CY7C4425
CY7C4205
CY7C4215
CY7C4225
CY7C4235
CY7C4245
2728 2930 3132 33 34 35 36 37 38 3940 4142 43
PAE
FL/RT
WEN
WXI
PAF
RXI
FF
WXO/HF
RXO
WCLK
GND
V
CC
V
CC
Q
0
Q
1
Q
2
Q
3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
FL/RT
WCLK
WEN
WXI
V
CC
PAF
RXI
FF
WXO/HF
RXO
PAE
Q
0
Q
1
GND
Q
2
42x5–2
2
Q
3
42X5–3
CYPRESS [ CYPRESS SEMICONDUCTOR ]
