CY7C68001
6.3
CY7C68001 Pin Definitions
Table 6-1.
SX2
Pin Definitions
QFN SSOP
Pin
Pin
3
6
9
8
42
5
10
13
16
15
49
12
Name
AVCC
AGND
DMINUS
DPLUS
RESET#
XTALIN
Type
Power
Power
I/O/Z
I/O/Z
Input
Input
Default
N/A
N/A
Z
Z
N/A
N/A
Description
Analog V
CC
. This signal provides power to the analog section of the chip.
Analog Ground.
Connect to ground with as short a path as possible.
USB D– Signal.
Connect to the USB D– signal.
USB D+ Signal.
Connect to the USB D+ signal.
Active LOW Reset.
Resets the entire chip. This pin is normally tied to V
CC
through a 100K resistor, and to GND through a 0.1-µF capacitor.
Crystal Input.
Connect this signal to a 24-MHz parallel-resonant, fundamental
mode crystal and 20-pF capacitor to GND. It is also correct to drive XTALIN with
an external 24-MHz square wave derived from another clock source.
Crystal Output.
Connect this signal to a 24-MHz parallel-resonant, fundamental
mode crystal and 20-pF capacitor to GND. If an external clock is used to drive
XTALIN, leave this pin open.
No Connect.
This pin must be left unconnected.
READY
is an output-only ready that gates external command reads and writes.
Active High.
INT#
is an output-only external interrupt signal. Active Low.
SLOE
is an input-only output enable with programmable polarity (POLAR.4) for
the slave FIFOs connected to FD[7:0] or FD[15:0].
FIFOADR2
is an input-only address select for the slave FIFOs connected to
FD[7:0] or FD[15:0].
FIFOADR0
is an input-only address select for the slave FIFOs connected to
FD[7:0] or FD[15:0].
FIFOADR1
is an input-only address select for the slave FIFOs connected to
FD[7:0] or FD[15:0].
PKTEND
is an input-only packet end with programmable polarity (POLAR.5) for
the slave FIFOs connected to FD[7:0] or FD[15:0].
FLAGD
is a programmable slave-FIFO output status flag signal. CS# is a master
chip select (default).
FD[0]
is the bidirectional FIFO/Command data bus.
FD[1]
is the bidirectional FIFO/Command data bus.
FD[2]
is the bidirectional FIFO/Command data bus.
FD[3]
is the bidirectional FIFO/Command data bus.
FD[4]
is the bidirectional FIFO/Command data bus.
FD[5]
is the bidirectional FIFO/Command data bus.
FD[6]
is the bidirectional FIFO/Command data bus.
FD[7]
is the bidirectional FIFO/Command data bus.
FD[8]
is the bidirectional FIFO data bus.
FD[9]
is the bidirectional FIFO data bus.
FD[10]
is the bidirectional FIFO data bus.
FD[11]
is the bidirectional FIFO data bus.
FD[12]
is the bidirectional FIFO data bus.
FD[13]
is the bidirectional FIFO data bus.
FD[14]
is the bidirectional FIFO data bus.
FD[15]
is the bidirectional FIFO data bus.
4
11
XTALOUT
Output
N/A
54
33
34
35
36
37
38
39
40
18
19
20
21
22
23
24
25
45
46
47
48
49
50
51
52
5
40
41
42
43
44
45
46
47
25
26
27
28
29
30
31
32
52
53
54
55
56
1
2
3
NC
READY
INT#
SLOE
FIFOADR2
FIFOADR0
FIFOADR1
PKTEND
Output
Output
Output
Input
Input
Input
Input
Input
O
L
H
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
FLAGD/C
CS#:I
S#
FLAGD:O
FD[0]
FD[1]
FD[2]
FD[3]
FD[4]
FD[5]
FD[6]
FD[7]
FD[8]
FD[9]
FD[10]
FD[11]
FD[12]
FD[13]
FD[14]
FD[15]
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Document #: 38-08013 Rev. *H
Page 12 of 42
CYPRESS [ CYPRESS SEMICONDUCTOR ]
