PRELIMINARY
W209C
Frequency Generator for Integrated Core Logic
with 133-MHz FSB
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Low jitter and tightly controlled clock skew
• Highly integrated device providing clocks required for
CPU, core logic, and SDRAM
• Two copies of CPU clock
• Nine copies of SDRAM clock
• Eight copies of PCI clock
• One copy of synchronous APIC clock
• Two copies of 66-MHz outputs
• Two copies of 48-MHz outputs
• One copy of selectable 24- or 48-MHz clock
• One copy of double strength 14.31818-MHz reference
clock
• Power-down control
• SMBus interface for turning off unused clocks
Table 1. Frequency Selections
FS4 FS3 FS2 FS1 FS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
75.3
95.0
129.0
150.0
150.0
110.0
140.0
144.0
68.3
105.0
138.0
140.0
66.8
100.2
133.6
133.6
157.3
160.0
146.6
122.0
127.0
122.0
117.0
114.0
80.0
78.0
166.0
160.0
66.6
100.0
133.3
133.3
SDRAM 3V66
113.0
95.0
129.0
113.0
150.0
110.0
140.0
108.0
102.5
105.0
138.0
105.0
100.2
100.2
133.6
100.2
118.0
120.0
110.0
91.5
127.0
122.0
117.0
114.0
120.0
117.0
166.0
160.0
100.0
100.0
133.3
100.0
75.3
63.3
86.0
75.3
73.0
93.3
72.0
68.3
70.0
92.0
70.0
66.8
66.8
89.1
66.8
78.6
80.0
73.3
61.0
84.6
81.3
78.0
76.0
80.0
78.0
55.3
53.3
66.6
66.6
88.9
66.6
PCI
37.6
31.6
43.0
37.6
36.6
46.7
36.0
34.1
35.0
46.0
35.0
33.4
33.4
44.4
33.4
39.3
40.0
36.6
30.5
42.3
40.6
39.0
38.0
40.0
39.0
27.6
26.7
33.3
33.3
44.4
33.3
APIC
18.8
15.8
21.5
18.8
25.0
18.3
23.3
18.0
17.0
17.5
23.0
17.5
16.7
16.7
22.2
16.7
19.6
20.0
18.3
15.2
21.1
20.3
19.5
19.0
20.0
19.5
13.8
13.3
16.6
16.6
22.2
16.6
SS
OFF
–0.6%
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
±0.45%
±0.45%
±0.45%
±0.45%
OFF
OFF
OFF
–0.6%
OFF
–0.6%
OFF
OFF
OFF
OFF
OFF
OFF
–0.6%
–0.6%
–0.6%
–0.6%
100.0 50.0
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter:................................................... 500 ps
CPU, 3V66 Output Skew: ........................................... 175 ps
SDRAM, APIC, 48-MHz Output Skew: ....................... 250 ps
PCI Output Skew: ....................................................... 500 ps
CPU to SDRAM Skew (@ 133 MHz) ....................... ± 0.5 ns
CPU to SDRAM Skew (@ 100 MHz) ................. 4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz)........................ 7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead) .......................... 1.5 to 3.5 ns
PCI to APIC Skew..................................................... ± 0.5 ns
Block Diagram
X1
X2
XTAL
OSC
PLL REF FREQ
VDDQ3
REF2X/FS3*
Pin Configuration
[1]
REF2x/FS3*
VDDQ3
X1
X2
GND
VDDQ3
3V66_0
3V66_1
GND
FS0*/PCI0
FS1*/PCI1
FS2*/PCI2
GND
PCI3
PCI4
VDDQ3
PCI5
PCI6
PCI7
GND
48MHz_0
FS4*/48MHz_1
SI0/24_48#MHz*
VDDQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDQ2
APIC
VDDQ2
CPU0
CPU1
GND
VDDQ3
SDRAM0
SDRAM1
SDRAM2
GND
SDRAM3
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
DCLK
GND
PWRDWN#
^
SCLK
VDDQ3
GND
SDATA
VDDQ2
SDATA
SCLK
SMBus
Logic
(FS0:4*)
Divider,
Delay,
and
Phase
Control
Logic
CPU0:1
2
APIC
VDDQ3
2
W209C
3V66_0:1
FS0*/PCI0
FS1*/PCI1
FS2*/PCI2
PLL 1
5
PCI3:7
SDRAM0:7
PWRDWN#
8
DCLK
VDDQ3
48MHz_0
PLL2
/2
FS4*/48MHz_1
SI0/24_48#MHz*
Note:
1. Internal pull-down or pull-up resistors present on inputs marked with
* or ^ respectively. Design should not rely solely on internal pull-up
or pull-down resistor to set I/O pins HIGH or LOW respectively.
Cypress Semiconductor Corporation
Document #: 38-07171 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 15, 2002
CYPRESS [ CYPRESS SEMICONDUCTOR ]
