W320-03
PWRDWN# Deassertion[15]
10-30 µs min.
100-200 µs max.
<3ms
66BUFF1/GMCH
66BUFF0,2
PCI
PCI_F (APIC)
PWR_DWN#
CPU
CPU#
3V66
66IN
USB
REF
PWRGD# Timing Diagrams
GND VRM 5/12V
PWRGD#
VID [3:0]
BSEL [1:0]
PWRGD# FROM
VRM
Possible glitch while Clock VCC is coming
up. Will be gone in 0.2–0.3 ms delay.
PWRGD# FROM
NPN
VCC CPU CORE
PWRGD#
Wait for
0.2 – 0.3 ms
delay
Sample
BSELS
PWRGD#
VCC W320 CLOCK
GEN
State 1 State 2
State 3
State 0
CLOCK STATE
OFF
ON
CLOCK VCO
OFF
ON
CLOCK OUTPUTS
Figure 2. CPU Power BEFORE Clock Power
Document #: 38-07248 Rev. *C
Page 12 of 18