Pin Description
Pin No
1
2
3
4
5
6
7
V+
CREF+
CREF-
CINT
CAZ
BUFF
RAZ
IVSH
IVSL
OVX
OHMC
OVH
OVSG
OR1
VR5
VR4
VR3
VR2
TEST5
ACVL
ACVH
ADI
ADO
ADOHZ
VRH
VR
VA+
VA-
ADP
SGND
OHMC1
VR1
VBAR
R9K
R1K
CA-
CA+
CSH+
CSH-
OHMC2
SLEEP
FREQ
RS232
DSHIFT
BKLIT
Symbol
Type
O
I/O
I/O
O
I
O
O
I
I
I
O
I
I
O
O
O
O
O
I/O
O
O
I
O
I
O
I
I
I
I
G
O
I
I
O
O
I/O
I/O
O
O
O
O
I
I
I
I
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
v2.61
Output of on-chip DC-DC converter.
Positive connection for reference capacitor.
Negative connection for reference capacitor.
Integrator output. Connect to integral capacitor
Auto-zero capacitor connection.
Buffer output pin. Connect to integral resistor
Buffer output pin in high-speed mode. Connect to high-speed integral
resistor.
High current measurement input.
Low current measurement input
Input high voltage for resistance measurement
Filter capacitor connection for resistance mode below 6.600MΩ
range.
Output connection for resistance measurement
Sense low voltage for resistance measurement
Reference resistor connection for 660.0Ω range
Voltage measurement ÷10000 attenuator(1000V)
Voltage measurement ÷1000 attenuator(660.0V)
Voltage measurement ÷100 attenuator(66.00V)
Voltage measurement ÷10 attenuator(6.600V)
Test pin
DC signal low input in ACV/ACA mode. Connect to negative output of
external AC to DC converter.
DC signal high input in ACV/ACA mode. Connect to positive output of
external AC to DC converter.
Negative input of internal AC to DC OP Amp.
Output of internal AC to DC OP Amp.
Frequency input under voltage/current mode, offset to AGND.
Output of band-gap voltage reference. Typically –1.2V
Reference input voltage connection. Typically –400mV
For ADP mode. De-integrating voltage positive input. The input should
be higher than VA-.
For ADP mode. De-integrating voltage negative input. The input should
be lower than VA+.
Measurement input in ADP mode.
Signal Ground.
Filter capacitor connection for resistance mode under 660.0KΩ
range.
Measurement input.
In capacitance mode, a compensation capacitor is connected.
In temperature mode, it is used to control decimal point.
In µA or mA modes, pull to V- to disable the ‘µ
2
’ or ‘m
2
’ sign on LCD.
Connect
to a precise 9KΩ resister.
Connect to a precise 1KΩ resister.
Negative auto-zero capacitor connection for capacitor measurement
Positive auto-zero capacitor connection for capacitor measurement
Positive connection to external capacitor.
Negative connection to external capacitor.
Filter capacitor connection for 6.600MΩ range in resistance mode.
Sleep mode indicator, asserts low in SLEEP mode.
Frequency counter input, offset V-/2 internally by the chip.
Assert low to enable serial data output.
Pull to V-
to have 0.01MΩ resolution in 66.00MΩ.
Pull to DGND or keep it float will change the resolution to 0.1MΩ.
Back light function. Pulse low to set BKOUT pin output.
3
10/09/27
Description
CYRUSTEK [ Cyrustek corporation ]
