CYStech Electronics Corp.
Figure 1: Open Loop Test Circuit
Spec. No. : C510P8
Issued Date : 2003.04.24
Revised Date :
Page No. : 5/15
VREF
RT
4.7k
2N2222
A
VREF
100k
ERROR AMP.
ADJUST
COMP
VFB
1k
ISENSE
ADJUST
ISENSE
5k
RT/CT
0.1uF
VI
1
2
8
7
VI
0.1uF
1W
1k
OUTPUT
3
4
6
5
4.7k
OUTPUT
GROUND
CT
GROUND
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass
capacitors should be connected close to pin 5 in a single point ground. The transistor and 5kΩ potentiometer are
used to sample the oscillator waveform and apply an adjustable ramp to pin 3.
Figure 2:Timing Resistor vs Oscillator Frequency
100
CT=100pF
200pF
100
Figure 3:Output Dead-Time vs Oscillator Frequency
CT=2nF
Output Dead Time---(%)
CT=1nF
10
CT=500p
F
CT=200pF
CT=10nF
CT=5nF
Timing Resistor---RT(kΩ)
500pF
10
10nF
5nF
2nF
1nF
CT=100pF
Vi=15V
TA=25
1
1
10
Vi=15V,TA=25
℃
100
Oscillator Frequency---fosc(kHz)
1000
10
100
Oscillator Frequency---fosc(kHz)
1000
PL384XBP8
CYStek Product Specification
CYSTEKEC [ CYSTECH ELECTONICS CORP. ]
