DS1220Y
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in a high impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high impedance state during this period.
9. Each DS1220Y is marked with a 4-digit date code AABB. AA designates the year of manufacture.
BB designates the week of manufacture. The expected t
DR
is defined as starting at the date of
manufacture.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.
11. In a power-down condition the voltage on any pin may not exceed the voltage of V
CC
.
12. t
WR1
, t
DH1
are measured from WE going high.
13. t
WR2
, t
DH2
are measured from CE going high.
14. DS1220Y modules are recognized by Underwriters Laboratory (U.L.
) under file E99151 (R).
DC TEST CONDITIONS
Outputs open.
All voltages are referenced to ground.
AC TEST CONDITIONS
Output Load: 100pF + 1TTL Gate
Input Pulse Levels: 0-3.0V
Timing Measurement Reference Levels
Input:1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
7 of 8
DALLAS [ DALLAS SEMICONDUCTOR ]
