DS12887
NONVOLATILE RAM
The 114 general purpose nonvolatile RAM bytes are not dedicated to any special function within the
DS12887. They can be used by the processor program as nonvolatile memory and are fully available
during the update cycle.
INTERRUPTS
The RTC plus RAM includes three separate, fully automatic sources of interrupt for a processor. The
alarm interrupt can be programmed to occur at rates from once per second to once per day. The periodic
interrupt can be selected for rates from 500 ms to 122
µs.
The update–ended interrupt can be used to
indicate to the program that an update cycle is complete. Each of these independent interrupt conditions is
described in greater detail in other sections of this text.
The processor program can select which interrupts, if any, are going to be used. Three bits in Register B
enable the interrupts. Writing a logic 1 to an interrupt-enable bit permits that interrupt to be initiated when
the event occurs. A 0 in an interrupt-enable bit prohibits the
IRQ
pin from being asserted from that
interrupt condition. If an interrupt flag is already set when an interrupt is enabled,
IRQ
is immediately set
at an active level, although the interrupt initiating the event may have occurred much earlier. As a result,
there are cases where the program should clear such earlier initiated interrupts before first enabling new
interrupts.
When an interrupt event occurs, the relating flag bit is set to logic 1 in Register C. These flag bits are set
independently of the state of the corresponding enable bit in Register B. The flag bit can be used in a
polling mode without enabling the corresponding enable bits. The interrupt flag bit is a status bit which
software can interrogate as necessary. When a flag is set, an indication is given to software that an
interrupt event has occurred since the flag bit was last read; however, care should be taken when using the
flag bits as they are cleared each time Register C is read. Double latching is included with Register C so
that bits which are set remain stable throughout the read cycle. All bits which are set (high) are cleared
when read and new interrupts which are pending during the read cycle are held until after the cycle is
completed. One, 2, or 3 bits can be set when reading Register C. Each utilized flag bit should be
examined when read to ensure that no interrupts are lost.
The second flag bit usage method is with fully enabled interrupts. When an interrupt flag bit is set and the
corresponding interrupt enable bit is also set, the
IRQ
pin is asserted low.
IRQ
is asserted as long as at
least one of the three interrupt sources has its flag and enable bits both set. The IRQF bit in Register C is
a 1 whenever the
IRQ
pin is being driven low. Determination that the RTC initiated an interrupt is
accomplished by reading Register C. A logic 1 in bit 7 (IRQF bit) indicates that one or more interrupts
have been initiated by the DS12887. The act of reading Register C clears all active flag bits and the IRQF
bit.
OSCILLATOR CONTROL BITS
When the DS12887 is shipped from the factory, the internal oscillator is turned off. This feature prevents
the lithium energy cell from being used until it is installed in a system. A pattern of 010 in bits 4 through
6 of Register A will turn the oscillator on and enable the countdown chain. A pattern of 11X will turn the
oscillator on, but holds the countdown chain of the oscillator in reset. All other combinations of bits 4
through 6 keep the oscillator off.
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DALLAS [ DALLAS SEMICONDUCTOR ]
