DS1385/DS1387
PERIODIC INTERRUPT SELECTION
The periodic interrupt will cause the IRQ pin to go to an
active state from once every 500 ms to once every
122
µs.
This function is separate from the alarm inter-
rupt which can be output from once per second to once
per day. The periodic interrupt rate is selected using the
same Register A bits which select the square wave fre-
quency (see Table 1). Changing the Register A bits af-
fects both the square wave frequency and the periodic
interrupt output. However, each function has a separate
enable bit in Register B. The SQWE bit controls the
square wave output. Similarly, the periodic interrupt is
enabled by the PIE bit in Register B. The periodic inter-
rupt can be used with software counters to measure in-
puts, create output intervals or await the next needed
software function.
There are three methods that can handle access of the
real–time clock that avoid any possibility of accessing
inconsistent time and calendar data. The first method
uses the update–ended interrupt. If enabled, an inter-
rupt occurs after every up date cycle that indicates that
over 999 ms are available to read valid time and date in-
formation. If this interrupt is used, the IRQF bit in Regis-
ter C should be cleared before leaving the interrupt rou-
tine.
A second method uses the update–in–progress bit
(UIP) in Register A to determine if the update cycle is in
progress. The UIP bit will pulse once per second. After
the UIP bit goes high, the update transfer occurs 244
µs
later. If a low is read on the UIP bit, the user has at least
244
µs
before the time/calendar data will be changed.
Therefore, the user should avoid interrupt service rou-
tines that would cause the time needed to read valid
time/calendar data to exceed 244
µs.
The third method uses a periodic interrupt to determine
if an update cycle is in progress. The UIP bit in Register
A is set high between the setting of the PF bit in Register
C (see Figure 3). Periodic interrupts that occur at a rate
of greater than t
BUC
allow valid time and date informa-
tion to be reached at each occurrence of the periodic in-
terrupt. The reads should be complete within
(t
PI
/2+t
BUC
) to ensure that data is not read during the up-
date cycle.
UPDATE CYCLE
The DS1385/DS1387 executes an update cycle once
per second regardless of the SET bit in Register B.
When the SET bit in Register B is set to one, the user
copy of the double buffered time, calendar and alarm by-
tes is frozen and will not update as the time increments.
However, the time countdown chain continues to update
the internal copy of the buffer. This feature allows time to
maintain accuracy independent of reading or writing the
time, calendar and alarm buffers and also guarantees
that time and calendar information is consistent. The up-
date cycle also compares each alarm byte with the cor-
responding time byte and issues an alarm if a match or if
a “don’t care” code is present in all three positions.
UPDATE–ENDED AND PERIODIC INTERRUPT RELATIONSHIP
Figure 3
UIP BIT IN
REGISTER A
t
BUC
UF BIT IN
REGISTER C
t
PI/2
t
PI/2
PF BIT IN
REGISTER C
t
PI
t
PI
= Periodic interrupt time interval per Table 1.
t
BUC
= Delay time before update cycle = 244
µs.
012496 8/20
DALLAS [ DALLAS SEMICONDUCTOR ]
