DS1643/DS1643P
DS1643 REGISTER MAP - BANK1 Table 2
DATA
B4
-
-
-
X
-
ADDRES
S
FUNCTION
B7
-
B6
-
B5
-
X
-
X
-
-
B3
-
-
-
X
-
B2
-
-
-
-
-
-
-
B1
-
-
-
-
-
-
-
B0
-
-
-
-
-
-
-
1FFF
1FFE
1FFD
1FFC
1FFB
1FFA
1FF9
YEAR
MONTH
DATE
00-99
01-12
01-31
01-07
00-23
00-59
00-59
A
X
X
X
X
X
X
X
FT
X
-
DAY
HOUR
-
-
-
-
MINUTES
SECONDS
CONTROL
-
-
OSC
1FF8
W
R
X
X
X
X
X
X
R = READ BIT
X = UNUSED
FT = FREQUENCY TEST
OSC = STOP BIT
= WRITE BIT
W
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1643 is in the read mode whenever WE (write enable) is high and CE (chip enable) is low. The
device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE
and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be
available at the latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the
data input/output pins (DQ) is controlled by CE and OE . If the outputs are activated before tAA , the data
lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE
remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1643 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or
write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low
the data bus can become active with read data defined by the address inputs. A low transition on WE will
then disable the outputs tWEZ after WE goes active.
DATA RETENTION MODE
When VCC is within nominal limits (VCC > 4.5 volts) the DS1643 can be accessed as described above with
read or write cycles. However, when VCC is below the power-fail point VPF (point at which write
protection occurs) the internal clock registers and RAM are blocked from access. This is accomplished
internally by inhibiting access via the CE signal. At this time the power-on reset output signal (RST ) will
be driven active low and will remain active until VCC returns to nominal levels. When VCC falls below the
level of the internal battery supply, power input is switched from the VCC pin to the internal battery and
clock activity, RAM, and clock data are maintained from the battery until VCC is returned to nominal
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DALLAS [ DALLAS SEMICONDUCTOR ]
