DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Table 2. Register Map
ADDRESS
7FFFF
7FFFE
7FFFD
7FFFC
7FFFB
7FFFA
7FFF9
7FFF8
OSC
= Stop Bit
W = Write Bit
DATA
B7
X
X
BF
X
X
OSC
W
B6
10 Year
X
X
FT
X
10 Month
10 Date
X
X
10 Hour
10 Minutes
10 Seconds
10 Century
R = Read Bit
X = See Note
B5
X
B4
B3
B2
Year
Month
Date
B1
B0
FUNCTION
Year
Month
Date
Day
Hour
Minutes
Seconds
Century
RANGE
00-99
01-12
01-31
01-07
00-23
00-59
00-59
00-39
X
Day
Hour
Minutes
Seconds
Century
FT = Frequency Test
BF = Battery Flag
R
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1744 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and
CE (chip enable) is low. The device architecture allows ripple-through access to any of the address
locations in the NV SRAM. Valid data is available at the DQ pins within t
AA
after the last address input is
stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times and
states are not met, valid data is available at the latter of chip-enable access (t
CEA
) or at output-enable access
time (t
OEA
). The state of the DQ pins is controlled by CE and OE . If the outputs are activated before t
AA
,
the data lines are driven to an intermediate state until t
AA
. If the address inputs are changed while CE and
OE remain valid, output data remains valid for output-data hold time (t
OH
) but then goes indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1744 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of t
WR
prior to the initiation of another read or
write cycle. Data in must be valid t
DS
prior to the end of write and remain valid for t
DH
afterward. In a
typical application, the OE signal is high during a write cycle. However, OE can be active provided that
care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low, the
data bus can become active with read data defined by the address inputs. A low transition on WE then
disables the output t
WEZ
after WE goes active.
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DALLAS [ DALLAS SEMICONDUCTOR ]
