DS1844
5-WIRE SERIAL INTERFACE
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Port Select Setup
R/
W
Setup
Clock Frequency
Width of CLK Pulse
Data Setup Time
Data Hold Time
Progapation Delay Time High to Low
Level Clock to Output
RST
High to Clock Input High
RST
Low from Clock Input High
RST
Inactive
(-40°C to +85°C; V
CC
=2.7V to 5.5V)
TYP
MAX
UNITS
ns
ns
5
MHz
ns
ns
ns
40
50
50
ns
ns
ns
ns
50
ns
SYMBOL
t
SETUP
t
SETUP
f
CLK
t
CH
t
DC
t
CDH
t
DV
t
CC
t
HLT
t
RLT
t
CR
MIN
30
30
DC
50
30
0
NOTES
14, 21
14, 21
14, 15
14, 15
14, 15
14, 15
14, 15
14, 15
14, 15
14, 15
14, 15
125
CLK Rise Time, CLK Fall Time
NOTES:
1.
2.
3.
4.
All voltages are referenced to ground.
I/O pins of fast mode devices must not obstruct the SDA and SCL lines if V
CC
is switched off.
I
CC
specified with SDA pin open.
I
STBY
specified with for V
CC
equal 3.0V and 5.0V and control port logic pins are driven to the
appropriate logic levels. Appropriate logic levels specify that logic inputs are within a 0.5-volt of
ground or V
CC
for the corresponding inactive state.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the
V
IH MIN
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of
the SCL.
A fast mode device can be used in a standard mode system, but the requirement t
SU:DAT
> 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line t
RMAX
+ t
SU:DAT
= 1000+250=1250 ns before the SCL line
is released.
C
B
- total capacitance of one bus line in picofarads, timing referenced to (0.9)(V
CC
) and (0.1)
(V
CC
).
Typical values are for ta = 25°C and nominal supply voltage.
5.
6.
7.
8.
9.
10.
9 of 14
101999
DALLAS [ DALLAS SEMICONDUCTOR ]
