DS21Q44
15. HDLC CONTROLLER FOR THE SA BITS OR DS0 ................................................................. 59
15.1
15.2
15.3
15.4
GENERAL OVERVIEW........................................................................................................... 59
HDLC STATUS REGISTERS .................................................................................................. 60
BASIC OPERATION DETAILS............................................................................................... 61
HDLC REGISTER DESCRIPTION.......................................................................................... 62
16. INTERLEAVED PCM BUS OPERATION ................................................................................... 69
17. JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT .......................... 72
17.1
17.2
17.3
17.4
DESCRIPTION.......................................................................................................................... 72
TAP CONTROLLER STATE MACHINE................................................................................ 73
INSTRUCTION REGISTER AND INSTRUCTIONS ............................................................. 75
TEST REGISTERS.................................................................................................................... 77
18. TIMING DIAGRAMS...................................................................................................................... 82
19. OPERATING PARAMETERS ...................................................................................................... 92
20. 128-PIN TQFP PACKAGE SPECIFICATIONS ........................................................................ 105
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DALLAS [ DALLAS SEMICONDUCTOR ]
