DS87C520/DS83C520
from 4 kB to 16 kB (1000h-3FFFh) is no longer located on-chip. This could result in code misalignment
and execution of an invalid instruction. The recommended method is to modify the ROMSIZE register
from a location in memory that will be internal (or external) both before and after the operation. In the
above example, the instruction which modifies the ROMSIZE register should be located below the 4 kB
(1000h) boundary, so that it will be unaffected by the memory modification. The same precaution should
be applied if the internal program memory size is modified while executing from external program
memory.
Off-chip memory is accessed using the multiple xed address/data bus on P0 and the MSB address on P2.
While serving as a memory bus, these pins are not I/O ports. This convention follows the standard 8051
method of expanding on-chip memory. Off-chip ROM access also occurs if the
EA
pin is a logic 0.
EA
overrides all bit settings. The
PSEN
signal will go active (low) to serve as a chip enable or output enable
when Ports 0 and 2 fetch from external ROM.
ROM MEMORY MAP
Figure 2
ROM SIZE ADJUSTABLE
DEFAULT = 16K BYTES
ROM SIZE IGNORED
DATA MEMORY ACCESS
Unlike many 8051 derivatives, the DS87C520/DS83C520 contains on-chip data memory. It also contains
the standard 256 bytes of RAM accessed by direct instructions. These areas are separate. The MOVX
instruction accesses the on-chip data memory. Although physically on-chip, software treats this area as
though it was located off- chip. The 1 kB of SRAM is between address 0000h and 03FFh.
Access to the on-chip data RAM is optional under software control. When enabled by software, the data
SRAM is between 0000h and 03FFh. Any MOVX instruction that uses this area will go to the on-chip
RAM while enabled. MOVX addresses greater tha n 03FFh automatically go to external memory through
Ports 0 and 2.
When disabled, the 1 kB memory area is transparent to the system memory map. Any MOVX directed to
the space between 0000h and FFFFh goes to the expanded bus on Ports 0 and 2. This also is the default
condition. This default allows the DS87C520/DS83C520 to drop into an existing system that uses these
addresses for other hardware and still have full compatibility.
The on-chip data area is software selectable using 2 bits in the Power Mana gement Register at location
C4h. This selection is dynamically programmable. Thus access to the on-chip area becomes transparent
to reach off-chip devices at the same addresses. The control bits are DME1 (PMR.1) and DME0
(PMR.0). They have the following operation:
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DALLAS [ DALLAS SEMICONDUCTOR ]
