DS87C520/DS83C520
DIP
30
PLCC
33
TQFP
27
SIGNAL
NAME
ALE
DESCRIPTION
ALE - Output.
The Address Latch Enable output
functions as a clock to latch the external address LSB from
the multiplexed address/data bus on Port 0. This signal is
commonly connected to the latch enable of an external 373
family transparent latch. ALE has a pulse width of 1.5
XTAL1 cycles and a period of four XTAL1 cycles. ALE is
forced high when the DS87C520/DS83C520 is in a Reset
condition. ALE can also be disabled and forced high by
writing
ALEOFF=1
(PMR.2).
ALE
operates
independently of ALEOFF during external memory
accesses.
Port 0 (AD0-7) - I/O.
Port 0 is an open-drain 8-bit bi-
directional I/O port. As an alternate function Port 0 can
function as the multiplexed address/data bus to access off-
chip memory. During the time when ALE is high, the LSB
of a memo ry address is presented. When ALE falls to a
logic 0, the port transitions to a bi-directional data bus.
This bus is used to read external ROM and read/write
external RAM memory or peripherals. When used as a
memory bus, the port provides active high drivers. The
reset condition of Port 0 is tri-state. Pullup resistors are
required when using Port 0 as an I/O port.
Port 1 - I/O.
Port 1 functions as both an 8-bit bi-
directional I/O port and an alternate functional interface
for Timer 2 I/O, new External Interrupts, and new Serial
Port 1. The reset condition of Port 1 is with all bits at a
logic 1. In this state, a weak pullup holds the port high.
This condition also serves as an input state, a weak pullup
holds the port high. This condition also serves as an input
mode, since any external circuit that writes to the port will
overcome the weak pullup. When software writes a 0 to
any port pin, the DS87C520/DS83C520 will activate a
strong pulldown that remains on until either a 1 is written
or a reset occurs. Writing a 1 after the port has been at 0
will cause a strong transition driver to turn on, followed by
a weaker sustaining pullup. Once the momentary strong
driver turns off, the port again becomes the output high
(and input) state. The alternate modes of Port 1 are out-
lines as follows.
Port
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Alternate
T2
T2EX
RXD1
TXD1
INT2
Function
External I/O for Timer/Counter 2
EX Timer/Counter 2
Capture/Reload Trigger
Serial Port 1 Input
Serial Port 1 Output
External Interrupt 2 (Positive Edge
Detect)
External Interrupt 3 (Negative
Edge Detect)
External Interrupt 4 (Positive Edge
Detect)
External Interrupt 5 (Negative
Edge Detect)
39
38
37
36
35
34
33
32
43
42
41
40
39
38
37
36
37
36
35
34
33
32
31
30
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
1-8
2-9
40-44
1-3
P1.0-P1.7
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
40
41
42
43
44
1
2
3
INT3
INT4
INT5
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DALLAS [ DALLAS SEMICONDUCTOR ]
