3D7110
APPLICATION NOTES (CONT’D)
custom reference designator
identifying the
intended frequency and duty cycle of operation.
The programmed delay accuracy of the device is
guaranteed, therefore, only for the user specified
input characteristics. Small input pulse width
variation about the selected pulse width will only
marginally impact the programmed delay
accuracy, if at all.
Nevertheless, it is strongly
recommended that the engineering staff at
DATA DELAY DEVICES be consulted.
circuitry to minimize the delay variations induced
by fluctuations in power supply and/or
temperature.
The
thermal coefficient
is reduced to
600
PPM/C,
which is equivalent to a variation , over
the 0C-70C operating range, of
±3%
from the
room-temperature delay settings and/or
1.0ns,
whichever is greater. The
power supply
coefficient
is reduced, over the 4.75V-5.25V
operating range, to
±1%
of the delay settings at
the nominal 5.0VDC power supply and/or
1.5ns,
whichever is greater.
It is essential that the
power supply pin be adequately bypassed
and filtered. In addition, the power bus
should be of as low an impedance
construction as possible. Power planes are
preferred.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D7110 programmable delay line
utilizes novel and innovative compensation
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
V
DD
V
IN
I
IN
T
STRG
T
LEAD
MIN
-0.3
-0.3
-1.0
-55
MAX
7.0
V
DD
+0.3
1.0
150
300
UNITS
V
V
mA
C
C
NOTES
25C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Current
Low Level Output Current
Output Rise & Fall Time
SYMBOL
I
DD
V
IH
V
IL
I
IH
I
IL
I
OH
I
OL
T
R
& T
F
MIN
2.0
0.8
1
1
-4.0
4.0
2
MAX
30
UNITS
mA
V
V
µA
µA
mA
mA
ns
NOTES
V
IH
= V
DD
V
IL
= 0V
V
DD
= 4.75V
V
OH
= 2.4V
V
DD
= 4.75V
V
OL
= 0.4V
C
LD
= 5 pf
*I
DD
(Dynamic) = 10 * C
LD
* V
DD
* F
where: C
LD
= Average capacitance load/tap (pf)
F = Input frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (C
LD
) = 25 pf max
Doc #96005
12/2/96
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
4
DATADELAY [ DATA DELAY DEVICES, INC. ]
