DDU8C
5-TAP, HCMOS-INTERFACED
FIXED DELAY LINE
(SERIES DDU8C)
FEATURES
•
•
•
•
•
•
Five equally spaced outputs
Fits standard 8-pin DIP socket
Low profile
Auto-insertable
Input & outputs fully CMOS interfaced & buffered
10 T
2
L fan-out capability
IN
T2
T4
GND
1
2
3
4
8
7
6
5
data
3
®
delay
devices,
inc.
PACKAGES
VDD
T1
T3
T5
IN
N/C
N/C
T2
N/C
T4
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VDD
N/C
T1
N/C
T3
N/C
T5
DDU8C-xx
DDU8C-xxA1
DDU8C-xxB1
DDU8C-xxM
DIP
Gull-Wing
J-Lead
Military DIP
Military SMD
DDU8C-xxMD1
DDU8C-xxMD4
FUNCTIONAL DESCRIPTION
The DDU8C-series device is a 5-tap digitally buffered delay line. The
signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an
amount determined by the device dash number (See Table). The total
delay of the line is measured from IN to T5. The nominal tap-to-tap delay
increment is given by one-fifth of the total delay.
PIN DESCRIPTIONS
IN
T1-T5
VDD
GND
Signal Input
Tap Outputs
+5 Volts
Ground
SERIES SPECIFICATIONS
•
•
•
•
•
•
Minimum input pulse width:
40% of total delay
Output rise time:
8ns typical
Supply voltage:
5VDC
±
5%
Supply current:
I
CCL
= 40µa typical
I
CCH
= 10ma typical
Operating temperature:
0° to 70° C
Temp. coefficient of total delay:
300 PPM/°C
DASH NUMBER SPECIFICATIONS
Part
Number
DDU8C-5050
DDU8C-5060
DDU8C-5075
DDU8C-5100
DDU8C-5125
DDU8C-5150
DDU8C-5175
DDU8C-5200
DDU8C-5250
Total
Delay (ns)
50
±
2.5
60
±
3.0
75
±
4.0
100
±
5.0
125
±
6.5
150
±
7.5
175
±
8.0
200
±
10.0
250
±
12.5
Delay Per
Tap (ns)
10.0
±
3.0
12.0
±
3.0
15.0
±
3.0
20.0
±
3.0
25.0
±
3.0
30.0
±
3.0
35.0
±
4.0
40.0
±
4.0
50.0
±
5.0
NOTE: Any dash number between 5004 and 5250
not shown is also available.
20%
20%
20%
20%
20%
VDD IN
T1
T2
T3
T4
T5 GND
DDU8C Functional diagram
©
1997 Data Delay Devices
Doc #97013
1/28/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
DATADELAY [ DATA DELAY DEVICES, INC. ]
