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PDU53-750 参数 Datasheet PDF下载

PDU53-750图片预览
型号: PDU53-750
PDF下载: 下载PDF文件 查看货源
内容描述: 3位, ECL -接口可编程延迟线(系列PDU53 ) [3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53)]
分类和应用: 延迟线光电二极管
文件页数/大小: 4 页 / 251 K
品牌: DATADELAY [ DATA DELAY DEVICES, INC. ]
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PDU53  
APPLICATION NOTES  
conditions are those for which the delay  
ADDRESS UPDATE  
tolerance specifications and monotonicity are  
guaranteed. The suggested conditions are  
those for which signals will propagate through the  
unit without significant distortion. The absolute  
conditions are those for which the unit will  
produce some type of output for a given input.  
The PDU53 is a memory device. As such,  
special precautions must be taken when  
changing the delay address in order to prevent  
spurious output signals. The timing restrictions  
are shown in Figure 1.  
When operating the unit between the  
After the last signal edge to be delayed has  
appeared on the OUT pin, a minimum time, TOAX  
is required before the address lines can change.  
This time is given by the following relation:  
recommended and absolute conditions, the  
delays may deviate from their values at low  
frequency. However, these deviations will  
remain constant from pulse to pulse if the input  
pulse width and period remain fixed. In other  
words, the delay of the unit exhibits frequency  
and pulse width dependence when operated  
beyond the recommended conditions. Please  
consult the technical staff at Data Delay Devices  
if your application has specific high-frequency  
requirements.  
,
TOAX = max { (Ai - A i-1) * TINC , 0 }  
where A i-1 and Ai are the old and new address  
codes, respectively. Violation of this constraint  
may, depending on the history of the input signal,  
cause spurious signals to appear on the OUT  
pin. The possibility of spurious signals persists  
until the required TOAX has elapsed.  
Please note that the increment tolerances listed  
represent a design goal. Although most delay  
increments will fall within tolerance, they are not  
guaranteed throughout the address range of the  
unit. Monotonicity is, however, guaranteed over  
all addresses.  
INPUT RESTRICTIONS  
There are three types of restrictions on input  
pulse width and period listed in the AC  
Characteristics table. The recommended  
PACKAGE DIMENSIONS  
16 15 14 13 12 11 10  
9
.600  
±.00  
.580  
MAX.  
.010  
±.002  
1
2
3
4
5
6
7
8
.870±.010  
Lead Material:  
Nickel-Iron alloy 42  
TIN PLATE  
.380  
MAX.  
.015 TYP.  
.070 MAX.  
.018  
TYP.  
.700±.010  
7 Equal spaces  
each .100±.010  
Non-Accumulative  
PDU53-xx (Commercial DIP)  
PDU53-xxM (Military DIP)  
Doc #98003  
3/18/98  
DATA DELAY DEVICES, INC.  
2
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com