DM8203
2-port switch with MII / RMII Interface
6. Control and Status Register Set
The DM8203 implements several control and status
registers, which can be accessed by the serial management
interface. These CSRs are byte aligned. All CSRs are set to
their default values by hardware or software reset unless
specified
Register
Description
Offset
Default value
after reset
00H
40H
XXH
EPCR
EPAR
EPDRL
EPDRH
VID
EEPROM & PHY Control Register
EEPROM & PHY Address Register
EEPROM & PHY Low Byte Data Register
EEPROM & PHY High Byte Data Register
Vendor ID
0BH
0CH
0DH
0EH
28H-29H
2AH-2BH
3AH
XXH
0A46H
8203H
21H
PID
P2FRV
Product ID
Port 2 driving capability Register
SWITCHCR SWITCH Control Register
VLANCR VLAN Control Register
SWITCHSR SWITCH Status Register
52H
53H
54H
00H
00H
00H
DSP1,2
P_INDEX
P_CTRL
P_STUS
P_RATE
P_BW
DSP Control Register I,II
Per Port Control/Status Index Register
Per Port Control Data Register
Per Port Status Data Register
Per Port Ingress and Egress Rate Control Register
Per Port Bandwidth Control Register
58H~59H
60H
61H
62H
66H
0000H
00H
00H
00H
00H
67H
00H
P_UNICAST Per Port Block Unicast ports Control Register
68H
00H
P_MULTI
P_BCAST
Per Port Block Multicast ports Control Register
Per Port Block Broadcast ports Control Register
69H
6AH
00H
00H
P_UNKNWN Per Port Block Unknown ports Control Register
P_PRI Per Port Priority Queue Control Register
6BH
6DH
00H
00H
VLAN_TAGL Per Port VLAN Tag Low Byte Register
VLAN_TAGH Per Port VLAN Tag High Byte Register
P_MIB_IDX Per Port MIB counter Index Register
6EH
6FH
80H
01H
00H
00H
MIB_DAT
MIB_DAT
MIB_DAT
MIB_DAT
PVLAN
MIB counter Data Register bit 0~7
MIB counter Data Register bit 8~15
MIB counter Data Register bit 16~23
MIB counter Data Register bit 24~31
Port-based VLAN mapping table registers
TOS Priority Map Register
81H
82H
83H
84H
B0-BFH
C0-CFH
D0-D1H
00H
00H
00H
00H
0FH
00H~FFH
50H,FAH
TOS_MAP
VLAN_MAP VLAN priority Map Register
Key to Default
In the register description that follows, the default column
takes the form:
<Reset Value>, <Access Type>
Where:
E = default value from EEPROM setting
T = default value from strap pin
<Access Type>:
RO = Read only
<Reset Value>:
RW = Read/Write
1
0
X
Bit set to logic one
Bit set to logic zero
No default value
R/C = Read and Clear
RW/C1=Read/Write and Cleared by write 1
WO = Write only
P = power on reset default value
H = hardware reset, by Reg. 52H bit 6, default value
Reserved bits should be written with 0.
Reserved bits are undefined on read access.
Preliminarydatasheet
DM8203-15-DS-P05
October 23, 2008
15
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
