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DM8203EP 参数 Datasheet PDF下载

DM8203EP图片预览
型号: DM8203EP
PDF下载: 下载PDF文件 查看货源
内容描述: 10/100 Mbps的双端口以太网交换机控制器, MII / RMII接口 [10/100 Mbps 2-port Ethernet Switch Controller With MII / RMII Interface]
分类和应用: 控制器以太网局域网(LAN)标准
文件页数/大小: 63 页 / 436 K
品牌: DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
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DM8203
2-port switch with MII / RMII Interface
1. General Description
The DM8203 is a fully integrated, high
performance, and cost-effective fast Ethernet switch
controller, two ports 10M/100Mbps PHY, and one
port MII, Reverse MII or RMII interface.
The DM8203 with two ports 10M/100Mbps PHY,
and one port MII, Reverse MII or RMII interface is a
fully integrated, high performance, and cost-effective
fast Ethernet switch controller
The internal memory of the DM8203 supports up to
1K uni-cast MAC address table, it is provided for
three ports’ usage. Each port of the DM8203 provides
four priorities transmit queues that can be defined by
port-based, 802.1p VLAN, or IP packet ToS field
automatically, to fit the various bandwidth and latency
requirement of data, voice, and video application.
Besides, it’s internal memory has three ports
usage, supporting up to 1K uni-case MAC address
table. Each port of DM8203 provides four priorities
transmit queens that can be defined by port-based,
802.1p VLAN, or IP packet ToS field automatically,
applies to the various bandwidth and latency
requirement of data, voice, and video application.
Each port also supports ingress and/or egress rate
control to provide proper bandwidth. And up to 16
groups of 802.1Q VLAN with Tag/Un-tag functions
are supported to provide efficient packet forwarding.
Each port, provide the MIB counters and loop-back
capability and the build in memory self test (BIST) for
system and board level diagnostic.
For proper bandwidth, each port also supports
ingress and/or egress rate control, and up to 16
groups of 802.1Q VLAN with Tag/Un-tag functions
support packet forwarding efficiently. Each port
provides the MIB counters, loop-back capability and
the build in memory self test (BIST) for system and
board level diagnostic.
The integrated two ports PHY are compliant with
IEEE 802.3u standards. The MII interface provides
the flexibility to connect Ethernet PHY, and it can be
configured to Reversed MII interface for SoC with MII
interface. An alternative interface, the RMII interface,
is also provided to connect the lower pin count
Ethernet PHY or SoC with RMII interface.
2. Block Diagram
Switch Engine
Switch Fabric
Port 0
MDI / MDIX
10/100M
PHY
10/100M
MAC
Embedded
Memory
Memory
BIST
Port 1
MDI / MDIX
10/100M
PHY
10/100M
MAC
Switch
Controller
Memory
Management
Port 2
MII / RMII
/ Reverse MII
10/100M
MAC
LED
Control
LEDs
SMI I/F
Control
Registers
MIB
Counters
EEPROM
Interface
EEPROM
8
Preliminary datasheet
DM8203-15-DS-P05
October 23, 2008