DM9006
2-port Switch with Processor Interface
6.5 RX Status Register (06H) .............................................................................................................................. 19
6.6 Receive Overflow Counter Register (07H) .................................................................................................. 19
6.7 Flow Control Register (0AH)......................................................................................................................... 19
6.8 EEPROM & PHY Control Register (0BH) ..................................................................................................... 19
6.9 EEPROM & PHY Address Register (0CH) ................................................................................................... 20
6.10 EEPROM & PHY Data Registers (0DH~0EH)............................................................................................. 20
6.11 Link Change Control Register (0FH) ......................................................................................................... 20
6.12 Processor Port Physical Address Registers (10H~15H) ......................................................................... 20
6.13 Processor Port Multicast Address Registers (16H~1DH)........................................................................ 20
6.14 RX Packet Length Low Register ( 20H ) .................................................................................................... 21
6.15 RX Packet Length High Register ( 21H ) ................................................................................................... 21
6.16 RX Additional Status Register ( 26H ) ....................................................................................................... 21
6.17 RX Additional Control Register ( 27H )...................................................................................................... 21
6.18 Vendor ID Registers (28H~29H) ................................................................................................................. 21
6.19 Product ID Registers (2AH~2BH) ............................................................................................................... 21
6.20 Chip Revision Register (2CH) .................................................................................................................... 21
6.21 Transmit Check Sum Control Register (31H) ........................................................................................... 21
6.22 Receive Check Sum Control Status Register (32H)................................................................................. 22
6.23 uP Data Bus driving capability Register (38H) ......................................................................................... 22
6.24 IRQ Pin Control Register (39H) .................................................................................................................. 22
Preliminary datasheet
DM9006-13-DS-P01
September 1, 2009
3
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
