DM9620
USB2.0 to Fast Ethernet Controller
CONTENT
1. Features:................................................................................................................................................ 7
1.1 System Description ..................................................................................................................... 8
2. Block Diagram and Block Description ................................................................................................. 9
3. Pin Configuration:............................................................................................................................... 10
3.1 64- Pin LQFP with MII Interface Mode ................................................................................... 10
3.2 64-pin Description .................................................................................................................... 11
3.2.1 MII Interfaces................................................................................................................. 11
3.2.2 RMII Interfaces.............................................................................................................. 11
3.2.3 Reverse MII Interfaces................................................................................................... 11
3.2.3 EEPROM Interface ........................................................................................................ 12
3.2.4 USB Interface................................................................................................................. 12
3.2.5 Clock Interface............................................................................................................... 12
3.2.6 LED Interface................................................................................................................. 12
3.2.7 10/100 PHY ................................................................................................................... 13
3.2.8 Miscellaneous ................................................................................................................ 13
3.2.9 Power ............................................................................................................................. 13
3.2.10 GPIO (TEST1 set to 1) ................................................................................................ 13
3.3 strap pins table .......................................................................................................................... 14
4. Vendor Control and Status Register Set ............................................................................................. 15
4.1 Network Control Register (00H) .............................................................................................. 16
4.2 Network Status Register (01H)................................................................................................. 17
4.3 TX Control Register (02H) ....................................................................................................... 18
4.4 RX Control Register ( 05H )..................................................................................................... 18
4.5 RX Status Register ( 06H ) ....................................................................................................... 19
4.6 Receive Overflow Counter Register ( 07H )............................................................................. 19
4.7 Back Pressure Threshold Register (08H).................................................................................. 20
4.8 Flow Control Threshold Register ( 09H ) ................................................................................. 20
4.9 RX/TX Flow Control Register ( 0AH ) .................................................................................... 21
4.10 EEPROM & PHY Control Register ( 0BH ) .......................................................................... 21
4.11 EEPROM & PHY Address Register ( 0CH ) ......................................................................... 22
4.12 EEPROM & PHY Data Register ( EE_PHY_L：0DH EE_PHY_H：0EH ) ............ 22
4.13 Wake Up Control Register ( 0FH ) ......................................................................................... 22
4.14 Physical Address Register ( 10H~15H )................................................................................. 22
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
2
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
