D8259
Programmable Interrupt Controller
ver 1.04
OVERVIEW
The D8259 is a soft Core of Programma-
ble Interrupt Controller. It is fully compatible
with the 82C59A device. The D8259 Core
manages up to 8-vectored priority interrupts
for processor. Programming it to cascade
allows for up to 64 vectored interrupts. More
than 64 vectored interrupts can be accom-
plished by programming to Poll Command
Mode.
D8259 can operate in all 82C59A modes,
and supports all 82C59A features:
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MCS-80/85 and 8088/8086 processor
modes
Fully nested mode and special fully
nested mode
Special mask mode
Buffered mode
Pool command mode
Cascade mode with master or slave se-
lection
Automatic end-of-interrupt mode
Specific and non-specific end-of-interrupt
commands
Automatic and Specific Rotation
Edge and level triggered interrupt input
modes
Reading of interrupt request register (IIR)
and in-service register (ISR) through data
bus.
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Writing and reading of interrupt mask reg-
ister (IMR) through data bus
KEY FEATURES
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8 vectored priority interrupts
Up to sixty-four vectored priority interrupts
with cascading
Support for all 82C59A modes features
MCS-80/85 and 8088/8086 processor
modes
Fully nested mode and special fully nested
mode
Special mask mode
Buffered mode
Pool command mode
Cascade mode with master or slave selec-
tion
Automatic end-of-interrupt mode
Specific and non-specific end-of-interrupt
commands
Automatic and Specific Rotation
Edge and level triggered interrupt input
modes
Reading of interrupt request register (IIR)
and in-service register (ISR) through data
bus
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Fully synthesizable, static design with no
internal tri-states
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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
