DF6811CPU
8-bit FAST Microcontrollers Family
ver 2.17
OVERVIEW
Document contains brief description of
DF6811CPU
core
functionality.
The
DF6811CPU is a advanced 8-bit MCU IP Core
with highly sophisticated, on chip peripheral
capabilities. DF6811CPU soft core is binary-
compatible with the industry standard 68HC11
8-bit microcontroller and can achieve a per-
formance
45-100 million instructions
per
second. There are two configurations of
DF6811CPU:
Harvard
where data and pro-
gram buses are separated, and
von Neu-
mann
with common program and data bus
DF6811CPU has FAST architecture that is 4.4
times faster compared to original implementa-
tion.
Self-monitoring circuitry is included on-chip
to protect against system errors. An illegal
opcode detection circuit provides a non-
maskable interrupt when illegal opcode de-
tected.
Two
software-controlled
power-saving
modes, WAIT and STOP, are available to
conserve additional power. These modes
make the DF6811CPU IP Core especially at-
tractive for automotive and battery-driven ap-
plications.
The DF6811CPU have built in the develop-
ment support features designed into DF6811.
The LIR signal is intended as a debugging aid.
This signal is driven to active low for the first
bus cycle of each new instruction, making it
easy to reverse assemble (disassemble) in-
structions from the display of a logic analyzer.
All trademarks mentioned in this document
are trademarks of their respective owners.
DF6811CPU is
fully customizable,
which
means it is delivered in the exact configuration
to meet users requirements.
There is no need
to pay extra for not used features and wasted
silicon.
It includes
fully automated testbench
with
complete set of tests
allowing easy
package validation at each stage of SoC de-
sign flow.
CPU FEATURES
FEATURES
●
●
●
●
●
●
●
●
●
●
●
FAST architecture, 4,4 times faster than
the original implementation
Software compatible with industry stan-
dard 68HC11
Configurable Harvard or Von Neumann
architectures
10 times faster multiplication
16 times faster division
256 bytes of remapped System Function
Registers space (SFRs)
Up to 16M bytes of Data Memory
De-multiplexed Address/Data Bus to allow
easy connection to memory
Two power saving modes: STOP, WAI
Ready pin allows Core to operate with
slow program and data memories
Fully synthesizable, static synchronous
design with no internal tri-states
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
