DI2CMS
I C Bus Interface – Master/Slave
ver 1.01
OVERVIEW
I
2
C is a two-wire, bi-directional serial bus that
provides a simple and efficient method of data
transmission over a short distance between
many devices. The DI2CMS core provides an
interface between a microprocessor / micro-
controller and an I
2
C bus. It can work as a
master or slave transmitter/receiver depend-
ing on working mode determined by micro-
processor/microcontroller. The DI2CMS core
incorporates all features required by the latest
I
2
C specification including clock synchroniza-
tion, arbitration, multi-master systems and
High-speed transmission mode. The DI2CMS
supports all the transmission speed modes.
Built-in timer allows operation from a wide
range of the clk frequencies.
The DI2CMS is a technology independent
VHDL or VERILOG design that can be imple-
mented in a variety of process technologies
and
can be fully customized accordingly to
customer needs
.
DI2CMS is delivered with
fully automated
testbench
and
complete set of tests
allow-
ing easy package validation at each stage of
SoC design flow.
○
2
Support for all transmission speeds
○
Standard (up to 100 kb/s)
○
Fast (up to 400 kb/s)
○
High Speed (up to 3,4 Mb/s)
○
○
○
○
○
Arbitration and clock synchronization
Support for multi-master systems
Support for both 7-bit and 10-bit addressing
formats on the I
2
C bus
Build-in 8-bit timer for data transfers speed
adjusting
User-defined timing (data setup, start setup,
start hold, etc.)
●
○
Slave mode
Slave operation
○
Slave transmitter
○
Slave receiver
○
Supports 3 transmission speed modes
○
Standard (up to 100 kb/s)
○
Fast (up to 400 kb/s)
○
High Speed (up to 3,4 Mb/s)
○
○
Allows operation from a wide range of input
clock frequencies
User-defined data setup time
KEY FEATURES
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●
○
Conforms to v.2.1 of the I
2
C specification
Master mode
Master operation
○
Master transmitter
○
Master receiver
●
●
●
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Simple interface allows easy connection to
microprocessor/microcontroller devices
Interrupt generation
Fully synthesizable
Static synchronous design with positive
edge clocking and synchronous reset
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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
