microcontroller is planned to use in portable
and power critical applications.
DoCD™ Debug Unit
– it’s a real-time hard-
ware debugger provides debugging capability
of a whole SoC system. In contrast to other on-
chip debuggers DoCD™ provides non-intrusive
debugging of running application. It can halt,
run, step into or skip an instruction, read/write
any contents of microcontroller including all
registers, internal, external, program memo-
ries, all SFRs including user defined peripher-
als. Hardware breakpoints can be set and con-
trolled on program memory, internal and exter-
nal data memories, as well as on SFRs. Hard-
ware breakpoint is executed if any write/read
occurred at particular address with certain data
pattern or without pattern. Two additional pins
CODERUN, DEBUGACS indicate the sate of
the debugger and CPU. CODERUN is active
when CPU is executing an instruction. DE-
BUGACS pin is active when any access is per-
formed by DoCD™ debugger. The DoCD™
system includes
JTAG interface
and complete
set of tools to communicate and work with core
in real time debugging. It is built as scalable
unit and some features can be turned off to
save silicon and reduce power consumption. A
special care on power consumption has been
taken, and when debugger is not used it is
automatically switched in power save mode.
Finally whole debugger is turned off when de-
bug option is no longer used.
tions per second (many instructions executed
in one clock cycle). The Off-chip Program
Memory located in address space between
1kB and 60kB, and above 64 kB is typically
used for main code and constants. This part of
the code is usually implemented as ROM,
SRAM or FLASH device. Because of relatively
long access time the program code executed
from mentioned above devices must be
fetched with additional Wait-States. Number of
required Wait-States depends on memory ac-
cess time and DP80390CPU clock frequency.
In most cases the proper number of Wait-
States cycles is between 2-5. The READY pin
can be also dynamically modulated e.g. by
SDRAM controller.
0x7FFFFF
Off chip Memory
(implemented as ROM,
SRAM or FLASH)
0x00FFFF
0x00F000
On chip Memory
(implemented as RAM)
Off chip Memory
(implemented as ROM,
SRAM or FLASH)
0x000400
0x000000
On-chip Memory
(implemented as ROM)
PROGRAM CODE SPACE
IMPLEMENTATION
The figure below shows an example Pro-
gram Memory space implementation in sys-
tems with DP80390CPU Microcontroller core.
The On-chip Program Memory located in ad-
dress space between 0kB and 1kB is typically
used for BOOT code with system initialization
functions. This part of the code is typically im-
plemented as ROM. The On-chip Program
Memory located in address space between
60kB and 64kB is typically used for timing criti-
cal part of the code e.g. interrupt subroutines,
arithmetic functions etc. This part of the code is
typically implemented as RAM and can be
loaded by the BOOT code during initialization
phase from Off-chip memory or through RS232
interface from external device. From the two
mentioned above spaces program code is
executed without wait-states and can achieve
a top performance up to 200 million instruc-
All trademarks mentioned in this document
are trademarks of their respective owners.
The figure below shows a typical Program
Memories connections in system with
DP80390CPU Microcontroller core.
prgramdatai
prgdatao
prgramwr
prgaddr
10
prgromdata
i
8
ASIC or FPGA
chip
8
Off-chip Memory
24
(implemented as
FLASH, or SRAM)
eg. 2-5 Wait-State
access
8
8
12
On-chip Memory
(implemented as RAM)
0 Wait-State access
On-chip Memory
(implemented as ROM)
0 Wait-State access
DP80390CPU
xdatai
xdatao
xaddr
xprgrd
xprgwr
ready
Wait-States
manager
The described above implementation should be
treated as an example. All Program Memory
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