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DP8051CPU 参数 Datasheet PDF下载

DP8051CPU图片预览
型号: DP8051CPU
PDF下载: 下载PDF文件 查看货源
内容描述: 流水线的高性能8位微控制器 [Pipelined High Performance 8-bit Microcontroller]
分类和应用: 微控制器
文件页数/大小: 10 页 / 256 K
品牌: DCD [ DIGITAL CORE DESIGN ]
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DP8051CPU
Pipelined High Performance
8-bit Microcontroller
ver 4.02
OVERVIEW
DP8051CPU is an
ultra high perform-
ance, speed optimized
soft core of a single-
chip 8-bit embedded controller dedicated for
operation with
fast
(typically on-chip) and
slow
(off-chip)
memories.
The core has been de-
signed with a special concern about
perform-
ance to power consumption
ratio. This ratio
is extended by an advanced power manage-
ment unit
PMU.
DP8051CPU soft core is 100% binary-
compatible with the industry standard 8051 8-
bit microcontroller. There are two configura-
tions of DP8051CPU:
Harward
where internal
data and program buses are separated, and
von Neumann
with common program and ex-
ternal data bus. DP8051CPU has Pipelined
RISC architecture
10 times faster
compared
to standard architecture and executes
85-200
million instructions
per second. This per-
formance can also be exploited to great advan-
tage in
low power
applications where the core
can be clocked over ten times more slowly
than the original implementation for no per-
formance penalty.
DP8051CPU is delivered with
fully auto-
mated testbench
and
complete set of tests
allowing easy package validation at each stage
of SoC design flow.
CPU FEATURES
100% software compatible with industry
standard 8051
Pipelined RISC architecture enables to
execute instructions 10 times faster com-
pared to standard 8051
24 times faster multiplication
12 times faster addition
Up to 256 bytes of internal (on-chip) Data
Memory
Up to 64K bytes of internal (on-chip) or
external (off-chip) Program Memory
Up to 16M bytes of external (off-chip) Data
Memory
User programmable Program Memory Wait
States solution for wide range of memories
speed
User programmable External Data Memory
Wait States solution for wide range of
memories speed
De-multiplexed Address/Data bus to allow
easy connection to memory
Dedicated signal for Program Memory
writes.
Interface for additional Special Function
Registers
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.