●
Fully synthesizable, static synchronous
design with positive edge clocking and no
internal tri-states
Scan test ready
2.0 GHz virtual
clock frequency in a 0.35u
technological process
CONFIGURATION
The following parameters of the DP8051CPU
core can be easy adjusted to requirements of
dedicated application and technology. Configu-
ration of the core can be prepared by effortless
changing appropriate constants in package file.
There is no need to change any parts of the
code.
•
•
•
•
Internal Program Memory
type
Internal Program ROM
Memory size
Internal Program RAM
Memory size
Internal Program Memory
fixed size
- synchronous
- asynchronous
-
0 - 64kB
-
-
0 - 64kB
-
- true
- false
-
subroutines
location
●
●
PERIPHERALS
●
○
DoCD™ debug unit
Processor execution control
Run
Halt
Step into instruction
Skip instruction
○
Read-write all processor contents
Program Counter (PC)
Program Memory
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
•
Interrupts
•
Power Management Mode
•
Stop mode
•
DoCD debug unit
- used
- unused
- used
- unused
- used
- unused
○
Hardware execution breakpoints
Program Memory
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
○
Hardware breakpoints activated at a certain
Program address (PC)
Address by any write into memory
Address by any read from memory
Address by write into memory a required data
Address by read from memory a required data
Besides mentioned above parameters all
available peripherals and external interrupts
can be excluded from the core by changing
appropriate constants in package file.
DELIVERABLES
♦
Source code:
◊
VHDL Source Code or/and
◊
VERILOG Source Code or/and
◊
Encrypted, or plain text EDIF netlist
♦
VHDL & VERILOG test bench environment
◊
Active-HDL automatic simulation macros
◊
ModelSim automatic simulation macros
◊
Tests with reference responses
♦
Technical documentation
◊
Installation notes
◊
HDL core specification
◊
Datasheet
♦
Synthesis scripts
♦
Example application
♦
Technical support
◊
IP Core implementation support
◊
3 months maintenance
●
●
●
○
Three wire communication interface
●
○
○
○
Power Management Unit
Power management mode
Switchback feature
Stop mode
●
○
○
Interrupt Controller
2 priority levels
2 external interrupt sources
Delivery the IP Core updates, minor and
major versions changes
Delivery the documentation updates
Phone & email support
http://www.DigitalCoreDesign.com
http://www.dcd.pl
All trademarks mentioned in this document
are trademarks of their respective owners.
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
