SYMBOL
clk
reset
ramdatai(7:0)
BLOCK DIAGRAM
clk
reset
Opcode
Decoder
sfrdatai(7:0)
ramdatao(7:0)
ramaddr(7:0)
ramoe
ramwe
sfrdatao(7:0)
sfraddr(7:0)
sfroe
sfrwe
prgdatao(7:0)
prgaddr(15:0)
prgramwr
xdatao(7:0)
xaddr(23:0)
xdataz
xdatard
xdatawr
xprgrd
xprgwr
ALU
prgromdatai(7:0)
prgramdatai(7:0)
xdatai(7:0)
ready
iprgromsize(2:0)
iprgramsize(2:0)
prgromdatai(7:0)
prgramdatai(7:0)
prgdatao(7:0)
prgaddr(15:0)
prgramwr
xdatai(7:0)
xdatao(7:0)
xramaddr(23:0)
xramdataz
xdatard
xdatawr
xprgrd
xprgwr
ready
ramdatai(7:0)
ramdatao(7:0)
ramaddr(7:0)
ramoe
ramwe
sfrdatai(7:0)
sfrdatao(7:0)
sfraddr(7:0)
sfroe
sfrwe
docddatai
docddatao
docdclk
Program
Memory
Interface
Control Unit
iprgromsize(2:0)
iprgramsize(2:0)
External
Memory
Interface
Interrupt
Controller
int0
int1
int2
int3
int4
int5
int6
port0i(7:0)
port1i(7:0)
port2i(7:0)
port3i(7:0)
port0o(7:0)
port1o(7:0)
port2o(7:0)
port3o(7:0)
Internal Data
Memory
Interface
I/O Ports
User SFR
Interface
int0
int1
int2
int3
int4
int5
int6
docddatai
docddatao
docdclk
stop
pmm
port0o(7:0)
port1o(7:0)
port2o(7:0)
port3o(7:0)
DoCD™
Debug Unit
Power
Management
Unit
stop
pmm
port0i(7:0)
port1i(7:0)
port2i(7:0)
port3i(7:0)
t0
gate0
t1
gate1
t2
t2ex
capture0
capture1
capture2
capture3
rxd0i
rxd1i
mscli
msdai
sscli
ssdai
ss
si
mi
scki
Floating
Point Unit
Multiply
Divide Unit
t2
t2ex
Timers 0 & 1
Timer 2
t0
gate0
t1
gate1
capture0
capture1
capture2
capture3
rxd1o
rxd1i
txd1
Compare
Capture Unit
Watchdog
Timer
UART 0
UART 1
rxd0o
rxd0i
txd0
so
si
mo
mi
scko
scki
sckz
ss
sso(7:0)
rxd0o
txd0
rxd1o
txd1
msclhs
msclo
msdao
ssclo
ssdao
sso(7:0)
so
mo
scko
sckz
msclhs
mscli
msclo
msdai
msdao
sscli
ssclo
ssdai
ssdao
Master
I2C Unit
SPI Unit
Slave
I2C Unit
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are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
