PERFORMANCE
The following tables give a survey about the
Core area and performance in ASICs Devices
(all key features have been included):
Device
0.25u typical
0.25u typical
Optimization
area
speed
F
max
100 MHz
200 MHz
40000
35000
30000
25000
20000
15000
10000
5000
0
80C51 (12MHz)
DR8051XP (200MHz)
268
1550
36996
Core performance in ASIC devices
For a user the most important is application
speed improvement. The most commonly used
arithmetic functions and their improvements
are shown in table below. An improvement was
computed as {80C51 clock periods} divided by
{DR8051XP clock periods} required to execute
an identical function. More details are available
in core documentation.
Function
8-bit addition (immediate
data)
8-bit addition (direct
addressing)
8-bit addition (indirect
addressing)
8-bit addition (register
addressing)
8-bit subtraction (immediate
data)
8-bit subtraction (direct
addressing)
8-bit subtraction (indirect
addressing)
8-bit subtraction (register
addressing)
8-bit multiplication
8-bit division
16-bit addition
16-bit subtraction
16-bit multiplication
32-bit addition
32-bit subtraction
32-bit multiplication
Average speed improvement:
Improvement
7,20
6,00
6,00
7,20
7,20
6,00
6,00
7,20
10,67
9,60
7,20
7,64
9,75
7,20
7,43
9,04
7,58
80C310 (33MHz)
Area utilized by the each unit of DR8051XP
core in vendor specific technologies is summa-
rized in table below.
Component
CPU*
DPTR1 register
DPTR0 decrement
DPTR1 decrement
DPTR0 & DPTR1 auto-switch
Timed Access protection
Area
[Gates]
[FFs]
4900
300
100
100
50
100
220
32
-
-
8
10
Interrupt Controller
INT2-INT6
500
350
40
25
Dhrystone Benchmark Version 2.1 was used to
measure Core performance. The following ta-
ble gives a survey about the DR8051XP per-
formance in terms of Dhrystone/sec and VAX
MIPS rating.
Device
80C51
80C310
DR8051XP
Target
-
-
0.25u
Clock
Dhry/sec
frequency
(VAX MIPS)
12 MHz
268 (0.153)
33 MHz
1550 (0.882)
200 MHz 36996 (21.000)
Power Management Unit
I/O ports
Timers
Timer 2
UART0
UART1
Master I2C Unit
Slave I2C Unit
SPI Unit
Compare Capture Unit
Watchdog Timer
Multiply Divide Unit
Total area
50
400
600
600
700
700
900
550
450
550
400
1700
14000
5
35
50
60
60
60
120
70
55
60
45
105
1060
*CPU – consisted of ALU, Opcode Decoder, Control Unit, Program &
Internal & External Memory Interfaces, User SFRs Interface
Core components area utilization
Core performance in terms of Dhrystones
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