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DNT04S0A0S03NFA 参数 Datasheet PDF下载

DNT04S0A0S03NFA图片预览
型号: DNT04S0A0S03NFA
PDF下载: 下载PDF文件 查看货源
内容描述: 负荷DC / DC电源模块非隔离点: 2.4 〜 5.5VIN , 0.75 〜 3.3Vo , 3A出 [Non-Isolated Point of Load DC/DC Power Modules: 2.4~5.5Vin, 0.75~3.3Vo, 3A out]
分类和应用: 电源电路
文件页数/大小: 13 页 / 1052 K
品牌: DELTA [ DELTA ELECTRONICS, INC. ]
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TEST CONFIGURATIONS
TO OSCILLOSCOPE
DESIGN CONSIDERATIONS
Input Source Impedance
V
I
(+)
To maintain low noise and ripple at the input voltage, it is
critical to use low ESR capacitors at the input to the
module. Figure 26 shows the input ripple voltage (mVp-p)
for various output models using 2x100 µF low ESR
tantalum
capacitor (KEMET p/n: T491D107M016AS,
AVX p/n: TAJD107M106R, or equivalent) in parallel with
47 µF ceramic capacitor (TDK p/n:C5750X7R1C476M or
equivalent). Figure 27 shows much lower input voltage
ripple when input capacitance is increased to 400 µF (4 x
100 µF)
tantalum
capacitors in parallel with 94 µF (2 x 47
µF) ceramic capacitor.
The input capacitance should be able to handle an AC
ripple current of at least:
L
2
100uF
Tantalum
BATTERY
V
I
(-)
Note:
Input reflected-ripple current is measured with a
simulated source inductance. Current is measured at the input
of the module.
Figure 23:
Input reflected-ripple test setup
COPPER STRIP
Irms
=
Iout
Input Ripple Voltage (mVp-p)
Vo
1uF
10uF
SCOPE
tantalum ceramic
Resistive
Load
Vout
Vout
1
Vin
Vin
Arms
60
52
44
36
28
20
0
1
2
3
4
GND
Note:
Use a 10µF tantalum and 1µF capacitor. Scope
measurement should be made using a BNC connector.
Figure 24:
Peak-peak output noise and startup transient
measurement test setup.
CONTACT AND
DISTRIBUTION LOSSES
Output Voltage (Vdc)
Figure 26:
Input voltage ripple for various output models, Io =
3A (CIN = 2
×
100µF tantalum // 47µF ceramic)
V
I
I
I
SUPPLY
Vo
Io
LOAD
Input Ripple Voltage (mVp-p)
40
36
32
28
24
20
0
1
2
3
4
GND
CONTACT RESISTANCE
Figure 25:
Output voltage and efficiency measurement test
setup
Note:
All measurements are taken at the module terminals.
When the module is not soldered (via socket), place
Kelvin connections at module terminals to avoid
measurement errors due to contact resistance.
Output Voltage (Vdc)
Figure 27:
Input voltage ripple for various output models, Io =
3A (CIN = 4
×
100µF tantalum // 2
×
47µF ceramic)
η
=
(
Vo
×
Io
)
×
100 %
Vi
×
Ii
DS_DNT04SMD3A_01182007
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