EL2150C EL2157C
125 MHz Single Supply Clamping Op Amps
Closed Loop AC Electrical Characteristics
(Notes 2
6) V
S
e a
5V GND
e
0V T
A
e
25 C V
CM
e a
1 5V V
OUT
e a
1 5V V
CLAMP
e a
5V V
ENABLE
e a
5V A
V
e a
1
e
0X R
L
e
150X to GND pin unless otherwise specified
R
F
Parameter
BW
Description
b
3 dB Bandwidth (V
OUT
e
400 mVp-p)
Conditions
V
S
e a
5V A
V
e a
1 R
F
e
0X
V
S
e a
5V A
V
eb
1 R
F
e
500X
V
S
e a
5V A
V
e a
2 R
F
e
500X
V
S
e a
5V A
V
e a
10 R
F
e
500X
V
S
e a
12V A
V
e a
1 R
F
e
0X
V
S
e a
3V A
V
e a
1 R
F
e
0X
Min Typ Max
125
60
60
6
150
100
25
30
20
60
55
200 275
300
28
10
32
40
75
0 05
0 05
48
1 25
50
25
7
Test
Units
Level
V
V
V
V
V
V
V
V
V
V
V
I
V
V
V
V
V
V
V
V
V
V
V
V
V
nV
0
Hz
pA
0
Hz
TD is 5 1in
ns
ns
ns
V
ms
V
ms
ns
%
ns
ns
ns
%
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
BW
g
0 1 dB Bandwidth (V
OUT
e
400 mVp-p) V
S
e a
12V A
V
e a
1 R
F
e
0X
V
S
e a
5V A
V
e a
1 R
F
e
0X
V
S
e a
3V A
V
e a
1 R
F
e
0X
GBWP
PM
SR
Gain Bandwidth Product
Phase Margin
Slew Rate
V
S
e a
12V
A
V
e a
10
R
L
e
1 kX CL
e
6 pF
V
S
e a
10V R
L
e
150X V
out
e
0V to
a
6V
V
S
e a
5V R
L
e
150X V
OUT
e
0V to
a
3V
t
R
t
F
OS
t
PD
t
S
Rise Time Fall Time
Overshoot
Propagation Delay
0 1% Settling Time
0 01% Settling Time
g
0 1V step
g
0 1V step
g
0 1V step
V
S
e
g
5V R
L
e
500X A
V
e a
1 V
OUT
e
g
3V
V
S
e
g
5V R
L
e
500X A
V
e a
1 V
OUT
e
g
3V
A
V
e a
2 R
F
e
1 kX
A
V
e a
2 R
F
e
1 kX
f
e
10 kHz
f
e
10 kHz
dG
dP
e
N
i
N
t
DIS
t
EN
t
CL
Note
Note
Note
Note
1
2
3
4
Differential Gain (Note 7)
Differential Phase (Note 7)
Input Noise Voltage
Input Noise Current
Disable Time (Note 8)
Enable Time (Note 8)
Clamp Overload Recovery
Note
Note
Note
Note
5
6
7
8
Internal short circuit protection circuitry has been built into the EL2150C EL2157C See the Applications section
CLAMP pin and ENABLE pin specifications apply only to the EL2157C
If the disable feature is not desired tie the ENABLE pin to the V
S
pin or apply a logic high level to the ENABLE pin
The maximum output voltage that can be clamped is limited to the maximum positive output Voltage or V
OP
Applying a
Voltage higher than V
OP
inactivates the clamp If the clamp feature is not desired either tie the CLAMP pin to the V
S
pin
or simply let the CLAMP pin float
The clamp accuracy is affected by V
IN
and R
L
See the Typical Curves Section and the Clamp Accuracy vs V
IN
R
L
curve
All AC tests are performed on a ‘‘warmed up’’ part except slew rate which is pulse tested
Standard NTSC signal
e
286 mVp-p f
e
3 58MHz as VIN is swept from 0 6V to 1 314V R
L
is DC coupled
Disable Enable time is defined as the time from when the logic signal is applied to the ENABLE pin to when the supply
current has reached half its final value
4
ELANTEC [ ELANTEC SEMICONDUCTOR ]
