EL2176C/EL2276C
70 MHz/1 mA Current Mode Feedback Amp w/Disable
DC Electrical Characteristics Ð Contd.
e
e
e
e
0V, T
A
g
V
S
5V, R
150X, ENABLE
25 C unless otherwise specified
§
L
Test
Parameter
Description
Conditions
Min Typ Max
Units
Level
e
g
g
g
V
Output Voltage Swing
Output Current
V
S
V
S
V
S
5
3.5
4.0
I
V
V
I
V
V
O
e a
e a
5 Single-Supply, High
5 Single-Supply, Low
4.0
0.3
100
55
1
V
I
O
EL2176C only
80
mA
mA
mA
mA
pF
kX
mA
mA
V
EL2276C only, per Amplifier
50
I
e
I
I
Supply Current
ENABLE
ENABLE
ENABLE
2.0V, per Amplifier
2
I
S
e
e
Supply Current (Disabled)
Output Capacitance (Disabled)
Enable Pin Input Resistance
Logic ‘‘1’’ Input Current
Logic ‘‘0’’ Input Current
4.5V
4.5V
0
20
I
S(DIS)
C
4.4
85
V
I
OUT(DIS)
e
R
Measured at ENABLE
2.0V, 4.5V
45
EN
e
e
b
0.04
I
IH
I
IL
Measured at ENABLE, ENABLE
Measured at ENABLE, ENABLE
4.5V
0V
V
V
I
b
53
V
Minimum Voltage at ENABLE to Disable
Maximum Voltage at ENABLE to Enable
4.5
DIS
EN
V
2.0
I
V
AC Electrical Characteristics
e
e
e
e
e
e
25 C unless otherwise specified
A
g
V
S
5V, R
R
1.0 kX, R
150X, ENABLE
0V, T
§
F
G
L
Parameter
Description
Conditions
Min Typ Max Test Level Units
b
b
e a
e a
e
3 dB BW
3 dB Bandwidth
3 dB Bandwidth
A
A
V
V
V
V
V
A
A
A
A
A
A
1
2
70
60
V
V
IV
V
V
V
V
V
V
V
V
I
MHz
MHz
V/ms
ns
V
b
b
3 dB BW
V
e a
V
g
SR
Slew Rate
2.5V, A
2
400
800
4.5
OUT
OUT
OUT
OUT
OUT
e
e
e
e
g
t , t
r
Rise and Fall Time
Propagation Delay
Overshoot
500 mV
500 mV
500 mV
f
g
t
4.5
ns
pd
g
OS
ts
3.0
%
e b
g
0.1% Settling
2.5V, A
1
40
ns
V
e a
e a
e a
e a
e a
e a
e
e
e
e
dG
dP
dG
dP
Differential Gain
Differential Phase
Differential Gain
Differential Phase
Turn-On Time
Turn-Off Time
2, R
2, R
1, R
1, R
2, V
2, V
150X (Note 1)
150X (Note 1)
500X (Note 1)
500X (Note 1)
0.15
0.15
0.02
0.01
40
%
V
V
V
V
V
V
L
L
L
L
§
%
§
e a
e a
e
e
e
t
t
1V, R
1V, R
150X (Note 2)
150X (Note 2)
100
ns
ns
dB
ON
OFF
IN
IN
L
L
1500 2000
85
I
CS
Channel Separation EL2276C only, f
5 MHz
V
e
Note 1: DC offset from 0V to 0.714V, AC amplitude 286 mV , f
P-P
3.58 MHz.
Note 2: Measured from the application of the logic signal until the output voltage is at the 50% point between initial and final
values.
3
ELANTEC [ ELANTEC SEMICONDUCTOR ]
