EL4095C
Video Gain Control Fader Multiplexer
Contd
Stray capacitance at each
b
V
IN
terminal should
absolutely be minimized especially in a positive-
gain mode or peaking will occur Similarly the
load capacitance should be minimized If more
than 25 pF of load capacitance must be driven a
load resistor from 100X to 400X can be added in
parallel with the output to reduce peaking but
some bandwidth degradation may occur A
‘‘snubber’’ load can alternatively be used This is
a resistor in series with a capacitor to ground
150X and 100 pF being typical values The ad-
vantage of a snubber is that it does not draw DC
load current A small series resistor low tens of
ohms can also be used to isolate reactive loads
Applications Information
If maximum bandwidth is not required distor-
tion can be reduced greatly (and signal voltage
range enlarged) by increasing the value of R
F
and any associated gain-setting resistor
100% Accuracies
When a channel gain is set to 100% static and
gain errors are similar to those of a simple CFA
The DC output error is expressed by
V
OUT
Offset
e
V
OS
A
V
a
(I
B
b
) R
F
The
gain
I
B
b
ally
input offset voltage scales with fed-back
but the bias current into the negative input
adds an error not dependent on gain Gener-
I
B
b
dominates up to gains of about seven
Distortion
The signal voltage range of the
a
V
IN
terminals
is within 3 5V of either supply rail
One must also consider the range of error cur-
rents that will be handled by the
b
V
IN
termi-
nals Since the
b
V
IN
of a CFA is the output of a
buffer which replicates the voltage at
a
V
IN
er-
ror currents will flow into the
b
V
IN
terminal
When an input channel has 100% gain assigned
to it only a small error current flows into its neg-
ative input when low gain is assigned to the
channel the output does not respond to the chan-
nel’s signal and large error currents flow
Here are a few idealized examples based on a
gain of
a
1 for channels A and B and R
F
e
1 kX
for different gain settings
Gain
100%
75%
50%
25%
0%
V
INA
1V
1V
1V
1V
1V
V
INB
0
0
0
0
0
I (
b
V
INA
)
0
b
250
mA
b
500
mA
b
750
mA
b
1 mA
The fractional gain error is given by
E
GAIN
e
(R
F
a
A
V
R
IN
b
) R
F
a
A
V
R
IN
) R
OL
The gain error is about 0 3% for a gain of one
and increases only slowly for increasing gain
R
IN
b
is the input impedance of the input stage
buffer and R
OL
is the transimpedance of the am-
plifier 80 kX and 350 kX respectively
Gain Control Inputs
The gain control inputs are differential and may
be biased at any voltage as long as V
GAIN
is less
than 2 5V below V
a
and 3V above V
b
The dif-
ferential input impedance is 5 5 kX and a com-
mon-mode impedance is more than 500 kX With
zero differential voltage on the gain inputs both
signal inputs have a 50% gain factor Nominal
calibration sets the 100% gain of V
INA
input at
a
0 5V of gain control voltage and 0% at
b
0 5V
of gain control V
INB
’s gain is complementary to
that of V
INA
a
0 5V of gain control sets 0% gain
at V
INB
and
b
0 5V gain control sets 100% V
INB
gain The gain control does not have a complete-
ly abrupt transition at the 0% and 100% points
There is about 10 mV of ‘‘soft’’ transfer at the
gain endpoints To obtain the most accurate
100% gain factor or best attenuation of 0% gain
it is necessary to overdrive the gain control input
by about 30 mV This would set the gain control
voltage range as
b
0 565 mV to
a
0 565V or
30 mV beyond the maximum guaranteed 0% to
100% range
12
I (
b
V
INB
)
1 mA
750
mA
500
mA
250
mA
0
V
OUT
1V
0 75V
0 5V
0 25V
0V
Thus either
b
V
IN
can receive up to 1 mA error
current for 1V of input signal and 1 kX feedback
resistors The maximum error current is 3 mA for
the EL4095 but 2 mA is more realistic The ma-
jor contributor of distortion is the magnitude of
error currents even more important than loading
effects The performance curves show distortion
versus input amplitude for different gains
ELANTEC [ ELANTEC SEMICONDUCTOR ]
