EL4584C
EL4584C
Horizontal Genlock 4 F
SC
Features
36 MHz general purpose PLL
4 F
SC
based timing (use the
EL4585 for 8 F
SC
)
Compatible w EL4583 Sync
Separator
VCXO Xtal or LC tank
oscillator
k
2 ns jitter (VCXO)
User controlled PLL capture and
lock
Compatible with NTSC and PAL
TV formats
8 pre-programmed TV scan rate
clock divisors
Selectable external divide for
custom ratios
Single 5V low current operation
General Description
The EL4584C is a PLL (Phase Lock Loop) sub system designed
for video applications but also suitable for general purpose use
up to 36 MHz In a video application this device generates a
TTL CMOS compatible Pixel Clock (Clk Out) which is a multi-
ple of the TV Horizontal scan rate and phase locked to it
The reference signal is a horizontal sync signal TTL CMOS
format which can be easily derived from an analog composite
video signal with the EL4583 Sync Separator An input signal
to ‘‘coast’’ is provided for applications were periodic distur-
bances are present in the reference video timing such as VTR
head switching The Lock detector output indicates correct lock
The divider ratio is four ratios for NTSC and four similar ratios
for the PAL video timing standards by external selection of
three control pins These four ratios have been selected for com-
mon video applications including 4 F
SC
3 F
SC
13 5 MHz
(CCIR 601 format) and square picture elements used in some
workstation graphics To generate 8 F
SC
6 F
SC
27 MHz (CCIR
601 format) etc use the EL4585 which includes an additional
divide by 2 stage
For applications where these frequencies are inappropriate or
for general purpose PLL applications the internal divider can be
bypassed and an external divider chain used
FREQUENCIES and DIVISORS
Function
Divisor
PAL Fosc (MHz)
Divisor
NTSC Fosc (MHz)
3Fsc
851
13 301
682
10 738
CCIR 601
864
13 5
858
13 5
Square
944
14 75
780
12 273
4Fsc
1135
17 734
910
14 318
Applications
Pixel Clock regeneration
Video compression engine
(MPEG) clock generator
Video capture or digitization
PIP (Picture in Picture) timing
generator
Text or graphics overlay timing
Ordering Information
Part No
Temp Range Package Outline
EL4584CN -40 C to
a
85 C 16-Pin DIP MDP0031
EL4584CS -40 C to
a
85 C 16-Lead SO MDP0027
CCIR 601 Divisors yield 720 pixels in the portion of each line for NTSC and PAL
Square pixels format gives 640 pixels for NTSC and 768 pixels for PAL in the active portion
3Fsc numbers do not yield integer divisors
For 6Fsc and 8Fsc clock frequencies see
EL4585 datasheet
Connection Diagram
EL4584 SO P-DIP Packages
Demo Board
A demo PCB is available for this
product Request ‘‘EL4584 5 Demo
Board’’
February 1995 Rev B
4584 – 17
Note
All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication however this data sheet cannot be a ‘‘controlled document’’ Current revisions if any to these
specifications are maintained at the factory and are available upon your request We recommend checking the revision level before finalization of your design documentation
4584C
1994 Elantec Inc
ELANTEC [ ELANTEC SEMICONDUCTOR ]
