HALIOS® MULTI-PURPOSE OPTICAL SENSOR WITH HIGH LIGHT IMMUNITY
E909.05
PRELIMINARY INFORMATION AUG 02, 2011
4.4.4.4
Receiver
Condition
Symbol
Rf
I
DC
V
KA
f
G
G
0
G
TOT
f
C
N
DEMOD
C
DIODE
V
REF
I
BIAS
1.22
10
-
1.25
22
30
130
125
1
-
70
Min.
70
Typ.
100
Max.
130
1000
Unit
kΩ
µA
V
kHz
dB
dBΩ
kHz
bit
pF
V
µA
No. Parameter
1
2
3
4
5
6
7
8
9
10
11
Transimpedance at ampli-
fier input (CA)
DC photo-current compens-
ation
Voltage at transimpedance
amplifier input
Corner frequency high pass
filter
Gain amplifier
Total gain
Center frequency
Resolution demodulator
output
Capacitance of photo diode
at input CA
Internal reference voltage
Internal reference current
Table 4.4.4.4.1 Receiver
5 Functional Description
5.1 Introduction
The general architecture of the 3D-optical input device is shown in the system block diagram.
The CPU is connected to the memory (FLASH and SRAM) and the peripheral modules via the internal sys-
tem bus. The system bus provides a 16 bit address space and allows 8 and 16 bit data transfers.
The memory contains the program code and the data. Memory and registers are mapped to the global
memory map and can be accessed through all memory related operation provided by the CPUs instruction
set.
The memory of the ASIC consists of a 16Kx16 (32KByte) flash cell and a 1.5Kx16 (3KByte) SRAM cell.
The Interrupt Controller collects requests from all interrupt sources and provides an interrupt signal to the
CPU. Interrupt sources can be masked within the interrupt controller. Interrupts are generated by the mod-
ules and hold until they are cleared within the module. See module description for clearing procedures.
The SPI can be configured either as a master or a slave. Transfer length is eight bit and can be extended by
a multiple of eight bit. Data FIFOs are provided for transmit and receive tasks.
The timer module contains a 32 bit timer module as well as a watchdog timer. Additionally a second timer
module operating on wakeup clock is implemented that remains active even in off mode, so it can be used for
a periodical wake up from off mode for applications that require a low current consumption.
6 IO port pins can either be configured as general purpose IO`s or can be configured as ports for the SPI or
JTAG module. Additionally two ports are reserved for the I
2
C slave interface.
This document contains information on a pre-production product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice.
ELMOS Semiconductor AG
Data Sheet 12 / 67
QM-No.: 25DS0014E.00
ELMOS [ ELMOS SEMICONDUCTOR AG ]
