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EBD11UD8ADDA-7B-E 参数 Datasheet PDF下载

EBD11UD8ADDA-7B-E图片预览
型号: EBD11UD8ADDA-7B-E
PDF下载: 下载PDF文件 查看货源
内容描述: 1GB DDR SDRAM SO- DIMM ( 128M字64位, 2级) [1GB DDR SDRAM SO-DIMM (128M words x64 bits, 2 Ranks)]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 19 页 / 213 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EBD11UD8ADDA-E
DC Characteristics 1 (TA = 0 to 70°C, VDD = 2.5V ± 0.2V, VSS = 0V)
Parameter
Operating current (ACTV-PRE)
Operating current
(ACTV-READ-PRE)
Idle power down standby current
Floating idle standby current
Quiet idle standby current
Active power down
standby current
Active standby current
Operating current
(Burst read operation)
Operating current
(Burst write operation)
Auto refresh current
Self refresh current
Operating current
(4 banks interleaving)
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7A
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
Grade
-6B
-7A, -7B
-6B
-7A, -7B
max.
1720
1520
2120
1840
48
480
400
320
320
1040
880
2520
2120
2520
2120
3080
2840
64
4600
3880
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Test condition
CKE
VIH,
tRC = tRC (min.)
CKE
VIH, BL = 4,
CL = 2.5,
tRC = tRC (min.)
CKE
VIL
Notes
1, 2, 9
1, 2, 5
4
CKE
VIH, /CS
VIH,
4, 5
DQ, DQS, DM = VREF
CKE
VIH, /CS
VIH,
4, 10
DQ, DQS, DM = VREF
CKE
VIL
CKE
VIH, /CS
VIH
tRAS = tRAS (max.)
CKE
VIH, BL = 2,
CL = 2.5
CKE
VIH, BL = 2,
CL = 2.5
tRFC = tRFC (min.),
Input
VIL or
VIH
Input
VDD – 0.2 V
Input
0.2 V
BL = 4
3
3, 5, 6
1, 2, 5, 6
1, 2, 5, 6
1, 5, 6, 7
Notes. 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one cycle.
6. DQ, DM, DQS transition twice per one cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycles.
10. Command/Address stable at
VIH or
VIL.
DC Characteristics 2 (TA = 0 to 70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
Parameter
Input leakage current
Output leakage current
Output high current
Output low current
Symbol
ILI
ILO
IOH
IOL
min.
–32
–10
–15.2
15.2
max.
32
10
Unit
µA
µA
mA
mA
Test condition
VDD
VIN
VSS
VDD
VOUT
VSS
VOUT = 1.95V
VOUT = 0.35V
1
1
Note
Note: 1. DDR SDRAM component specification.
Data Sheet E0603E10 (Ver. 1.0)
11