DATA SHEET
2GB Registered DDR2 SDRAM DIMM
EBE20RE4ABFA (256M words
×
72 bits, 1 Rank)
Specifications
•
Density: 2GB
•
Organization
256M words
×
72 bits, 1 rank
•
Mounting 18 pieces of 1G bits DDR2 SDRAM sealed
in FBGA
•
Package: 240-pin socket type dual in line memory
module (DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free (RoHS compliant)
•
Power supply: VDD
=
1.8V
±
0.1V
•
Data rate: 667Mbps/533Mbps/400Mbps (max.)
•
Eight internal banks for concurrent operation
(components)
•
Interface: SSTL_18
•
Burst lengths (BL): 4, 8
•
/CAS Latency (CL): 3, 4, 5
•
Precharge: auto precharge option for each burst
access
•
Refresh: auto-refresh, self-refresh
•
Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C
≤
TC
≤ +85°C
3.9µs at
+85°C <
TC
≤ +95°C
•
Operating case temperature range
TC = 0°C to +95°C
Features
•
Double-data-rate architecture; two data transfers per
clock cycle
•
The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
•
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
•
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
referenced to both edges of DQS
•
Posted /CAS by programmable additive latency for
better command and data bus efficiency
•
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
•
/DQS can be disabled for single-ended Data Strobe
operation
•
1 piece of PLL clock driver, 2 pieces of register driver
and 1 piece of serial EEPROM (2K bits EEPROM) for
Presence Detect (PD)
Document No. E0873E40 (Ver. 4.0)
Date Published December 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2006-2007
ELPIDA [ ELPIDA MEMORY ]
