PRELIMINARY DATA SHEET
128M bits DDR SDRAM
EDD1216AASE (8M words
×
16 bits)
Description
The EDD1216AASE is a 128M bits Double Data Rate
(DDR) SDRAM organized as 2,097,154 words
×
16 bits
×
4 banks. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 2 bits prefetch-
pipelined architecture. Data strobe (DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. It is packaged in 60-ball FBGA
(µBGA
) package.
Pin Configurations
/xxx indicates active low signal.
60-ball FBGA ( BGA)
1
A
VSSQ DQ15 VSS
VDD
DQ0 VDDQ
2
3
4
5
6
7
8
9
B
DQ14 VDDQ DQ13
DQ2 VSSQ DQ1
DQ4 VDDQ DQ3
DQ6 VSSQ DQ5
LDQS VDDQ DQ7
LDM
/WE
/RAS
BA1
A0
A2
VDD
VDD
/CAS
/CS
BA0
A10
A1
A3
NC
C
DQ12 VSSQ DQ11
D
DQ10 VDDQ DQ9
Features
•
Power supply : VDDQ = 2.5V
±
0.2V
: VDD = 2.5V
±
0.2V
•
Data rate: 333Mbps/266Mbps (max.)
•
Double Data Rate architecture; two data transfers per
clock cycle
•
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
•
Data inputs, outputs, and DM are synchronized with
DQS
•
4 internal banks for concurrent operation
•
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
•
Data mask (DM) for write data
•
Auto precharge option for each burst access
•
SSTL_2 compatible I/O
•
Programmable burst length (BL): 2, 4, 8
•
Programmable /CAS latency (CL): 2, 2.5
•
Programmable output driver strength: normal/weak
•
Refresh cycles: 4096 refresh cycles/64ms
15.6µs maximum average periodic refresh interval
•
2 variations of refresh
Auto refresh
Self refresh
•
FBGA (µBGA) package with lead free solder
(Sn-Ag-Cu)
Document No. E0614E20 (Ver. 2.0)
Date Published March 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
E
DQ8 VSSQ UDQS
F
VREF VSS
UDM
/CK
CKE
A9
A7
A5
VSS
G
CK
H
NC
J
A11
K
A8
(AP)
L
A6
M
A4
(Top view)
A0 to A11
BA0, BA1
DQ0 to DQ15
UQQS/LDQS
/CS
/RAS
/CAS
/WE
UDM/LDM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe
Column address strobe
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Elpida
Memory, Inc. 2004-2005
ELPIDA [ ELPIDA MEMORY ]
