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EDD1232ACBH-5B-F 参数 Datasheet PDF下载

EDD1232ACBH-5B-F图片预览
型号: EDD1232ACBH-5B-F
PDF下载: 下载PDF文件 查看货源
内容描述: 128M比特DDR SDRAM [128M bits DDR SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 51 页 / 633 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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DATA SHEET
128M bits DDR SDRAM
EDD1232ACBH (4M words
×
32 bits)
Specifications
Density: 128M bits
Organization
1M words
×
32 bits
×
4 banks
Package: 144-ball FBGA
Lead-free (RoHS compliant) and Halogen-free
Power supply: VDD, VDDQ
=
2.5V
−0.125V/+0.2V
Data rate: 400Mbps (max.)
Four internal banks for concurrent operation
Interface: SSTL_2
Burst lengths (BL): 2, 4, 8
Burst type (BT):
Sequential (2, 4, 8)
Interleave (2, 4, 8)
/CAS Latency (CL): 3
Precharge: auto precharge option for each burst
access
Driver strength: weak/matched
Refresh: auto-refresh, self-refresh
Features
• ×32
organization
Double-data-rate architecture; two data transfers per
clock cycle
The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
Data inputs, outputs, and DM are synchronized with
DQS
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Refresh cycles: 4096 cycles/32ms
Average refresh period: 7.8µs
Operating ambient temperature range
TA = 0°C to +70°C
Document No. E1202E20 (Ver.2.0)
Date Published October 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2008