EDD2508AETA, EDD2516AETA
AC Characteristics (TA = 0°C to +70°C, VDD, VDDQ = 2.6V ± 0.1V, VSS, VSSQ = 0V) [DDR400]
-5B
min.
5
-5C
min.
5
Parameter
Symbol
tCK
max.
8
max.
8
Unit Notes
Clock cycle time
CK high-level width
CK low-level width
ns
10
tCH
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tCK
tCL
min
(tCH, tCL)
min
(tCH, tCL)
CK half period
tHP
—
—
tCK
DQ output access time from CK, /CK
DQS output access time from CK, /CK
DQS to DQ skew
tAC
–0.7
–0.55
—
0.7
–0.7
–0.55
—
0.7
ns
ns
ns
ns
ns
2, 11
2, 11
3
tDQSCK
tDQSQ
tQH
0.55
0.4
0.55
0.4
DQ/DQS output hold time from DQS
Data hold skew factor
tHP – tQHS —
tHP – tQHS —
tQHS
—
0.5
—
0.5
Data-out high-impedance time
tHZ
tLZ
—
0.7
0.7
—
0.7
0.7
ns
ns
5, 11
6, 11
from CK, /CK
Data-out low-impedance time
from CK, /CK
–0.7
–0.7
Read preamble
tRPRE
tRPST
tDS
0.9
0.4
0.4
0.4
1.75
0
1.1
0.6
—
0.9
0.4
0.4
0.4
1.75
0
1.1
0.6
—
tCK
tCK
ns
Read postamble
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input pulse width
Write preamble setup time
Write preamble
8
8
7
tDH
—
—
ns
tDIPW
tWPRES
tWPRE
tWPST
—
—
ns
—
—
ns
0.25
0.4
0.72
0.2
0.2
0.35
0.35
0.6
0.6
2.2
2
—
0.25
0.4
0.72
0.2
0.2
0.35
0.35
0.6
0.6
2.2
2
—
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
Write postamble
0.6
1.28
—
0.6
1.28
—
9
Write command to first DQS latching transition tDQSS
DQS falling edge to CK setup time
DQS falling edge hold time from CK
DQS input high pulse width
tDSS
tDSH
tDQSH
tDQSL
tIS
—
—
—
—
DQS input low pulse width
—
—
Address and control input setup time
Address and control input hold time
Address and control input pulse width
Mode register set command cycle time
Active to Precharge command period
—
—
8
8
7
tIH
—
—
ns
tIPW
tMRD
tRAS
—
—
ns
—
—
tCK
ns
40
120000
—
40
120000
—
Active to Active/Auto-refresh command period tRC
Auto-refresh to Active/Auto-refresh command
period
55
60
ns
tRFC
70
—
70
—
ns
Active to Read/Write delay
tRCD
tRP
15
—
—
—
—
—
18
—
—
—
—
—
ns
ns
ns
ns
ns
Precharge to active command period
Active to Autoprecharge delay
Active to active command period
Write recovery time
15
18
tRAP
tRRD
tWR
tRCD min.
tRCD min.
10
15
10
15
Auto precharge write recovery and precharge
time
(tWR/tCK)+
(tRP/tCK)
(tWR/tCK)+
(tRP/tCK)
tDAL
—
—
tCK
13
Internal write to Read command delay
tWTR
tREF
2
—
2
—
tCK
µs
Average periodic refresh interval
—
7.8
—
7.8
Data Sheet E0859E50 (Ver. 5.0)
8
ELPIDA [ ELPIDA MEMORY ]
