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EDD2508AMTA-5C 参数 Datasheet PDF下载

EDD2508AMTA-5C图片预览
型号: EDD2508AMTA-5C
PDF下载: 下载PDF文件 查看货源
内容描述: 256M比特DDR SDRAM [256M bits DDR SDRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器双倍数据速率
文件页数/大小: 34 页 / 374 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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PRELIMINARY DATA SHEET
256M bits DDR SDRAM
EDD2508AMTA-5 (32M words
×
8 bits, DDR400)
EDD2516AMTA-5 (16M words
×
16 bits, DDR400)
Description
The EDD2508AMTA-5 is a 256M bits Double Data
Rate (DDR) SDRAM organized as 8,388,608 words
×
8
bits
×
4 banks. The EDD2516AMTA-5 is a 256M bits
DDR SDRAM organized as 4,194,304 words
×
16 bits
×
4 banks. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 2 bits prefetch-
pipelined architecture. Data strobe (DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode resister,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. They are packaged in standard 66-
pin plastic TSOP (II).
Pin Configurations
/xxx indicates active low signal.
66-pin plastic TSOP(II)
VDD
VDD
DQ0
DQ0
VDDQ VDDQ
NC
DQ1
DQ1
DQ2
VSSQ VSSQ
NC
DQ3
DQ2
DQ4
VDDQ VDDQ
NC
DQ5
DQ3
DQ6
VSSQ VSSQ
NC
DQ7
NC
NC
VDDQ VDDQ
NC LDQS
NC
NC
VDD
VDD
NC
NC
NC
LDM
/WE
/WE
/CAS
/CAS
/RAS
/RAS
/CS
/CS
NC
NC
BA0
BA0
BA1
BA1
A10(AP) A10(AP)
A0
A0
A1
A1
A2
A2
A3
A3
VDD
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS VSS
DQ15 DQ7
VSSQ VSSQ
DQ14 NC
DQ13 DQ6
VDDQ VDDQ
DQ12 NC
DQ11 DQ5
VSSQ VSSQ
DQ10 NC
DQ9 DQ4
VDDQ VDDQ
DQ8 NC
NC
NC
VSSQ VSSQ
UDQS DQS
NC
NC
VREF VREF
VSS VSS
UDM DM
/CK /CK
CK
CK
CKE CKE
NC
NC
A12 A12
A11 A11
A9
A9
A8
A8
A7
A7
A6
A6
A5
A5
A4
A4
VSS VSS
EO
Features
2.6 V power supply: VDDQ = 2.6V
±
0.1V
: VDD = 2.6V
±
0.1V
Data rate: 400Mbps (max.)
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs, outputs, and DM are synchronized with
DQS
4 internal banks for concurrent operation
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Auto precharge option for each burst access
2.5 V (SSTL_2 compatible) I/O
Programmable burst length (BL): 2, 4, 8
Programmable /CAS latency (CL): 3
Refresh cycles: 8192 refresh cycles/64ms
7.8μs maximum average periodic refresh interval
2 variations of refresh
Auto refresh
Self refresh
Document No. E0406E10 (Ver. 1.0)
Date Published September 2003 (K) Japan
URL: http://www.elpida.com
L
od
Pr
X 16
X8
A0 to A12
BA0, BA1
DQ0 to DQ15
(Top view)
DQS, UDQS, LDQS
/CS
/RAS
/CAS
/WE
DM, UDM, LDM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
This product became EOL in March, 2007.
©Elpida
Memory, Inc. 2003
t
uc