DATA SHEET
256M bits DDR SDRAM
EDD2508ARTA-5B (32M words
×
8 bits, DDR400)
Description
The EDD2508ARTA is a 256M bits Double Data Rate
(DDR) SDRAM organized as 8,388,608 words
×
8 bits
×
4 banks. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 2 bits prefetch-
pipelined architecture. Data strobe (DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode resister,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. They are packaged in standard 66-
pin plastic TSOP (II).
Pin Configurations
/xxx indicates active low signal.
66-pin Plastic TSOP(II)
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10(AP)
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
EO
Features
•
Power supply: VDD, VDDQ = 2.6V
±
0.1V
•
Data rate: 400Mbps (max.)
•
Double Data Rate architecture; two data transfers per
clock cycle
•
Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
•
Data inputs, outputs, and DM are synchronized with
DQS
•
4 internal banks for concurrent operation
•
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
•
Data mask (DM) for write data
•
Auto precharge option for each burst access
•
SSTL_2 compatible I/O
•
Programmable burst length (BL): 2, 4, 8
•
Programmable /CAS latency (CL): 3
•
Refresh cycles: 8192 refresh cycles/64ms
⎯
7.8μs maximum average periodic refresh interval
•
2 variations of refresh
⎯
Auto refresh
⎯
Self refresh
Document No. E0772E10 (Ver. 1.0)
Date Published July 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
L
od
Pr
A0 to A12
BA0, BA1
DQS
/CS
/RAS
/CAS
/WE
DM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
DQ0 to DQ7
(Top view)
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
This product became EOL in March, 2007.
©Elpida
Memory, Inc. 2005
t
uc