EDD2516ARTA-6B
DC Characteristics 1 (TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
Parameter
Symbol
IDD0
Grade
max.
85
Unit
mA
Test condition
Notes
1, 2, 9
CKE ≥ VIH,
tRC = tRC (min.)
Operating current (ACT-PRE)
CKE ≥ VIH, BL = 4,
Operating current
(ACT-READ-PRE)
IDD1
125
mA
CL = 2.5,
1, 2, 5
tRC = tRC (min.)
Idle power down standby current
Floating idle standby current
IDD2P
IDD2F
6
mA
mA
CKE ≤ VIL
CKE ≥ VIH, /CS ≥ VIH
DQ, DQS, DM = VREF
4
35
4, 5
CKE ≥ VIH, /CS ≥ VIH
Quiet idle standby current
Active power down standby current
Active standby current
IDD2Q
IDD3P
IDD3N
35
25
45
mA
mA
mA
4, 10
3
DQ, DQS, DM = VREF
CKE ≤ VIL
CKE ≥ VIH, /CS ≥ VIH
tRAS = tRAS (max.)
3, 5, 6
Operating current
CKE ≥ VIH, BL = 2,
IDD4R
IDD4W
IDD5
250
200
145
3
mA
mA
mA
mA
mA
1, 2, 5, 6
1, 2, 5, 6
(Burst read operation)
CL = 2.5
Operating current
(Burst write operation)
CKE ≥ VIH, BL = 2,
CL = 2.5
tRFC = tRFC (min.),
Input ≤ VIL or ≥ VIH
Input ≥ VDD – 0.2 V
Input ≤ 0.2 V
Auto Refresh current
Self refresh current
IDD6
Operating current
(4 banks interleaving)
IDD7A
330
BL = 4
1, 5, 6, 7
Notes: 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one clock cycle.
6. DQ, DM and DQS transition twice per one clock cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycle.
10. Command/Address stable at ≥ VIH or ≤ VIL.
DC Characteristics 2 (TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
Parameter
Symbol
ILI
min.
–2
max.
2
Unit
µA
Test condition
Notes
Input leakage current
Output leakage current
Output high current
Output low current
VDD ≥ VIN ≥ VSS
VDDQ ≥ VOUT ≥ VSS
VOUT = 1.95V
ILO
–5
5
µA
IOH
IOL
–16.2
16.2
—
—
mA
mA
VOUT = 0.35V
Data Sheet E0848E10 (Ver. 1.0)
6
ELPIDA [ ELPIDA MEMORY ]
