EDD5104ADTA, EDD5108ADTA, EDD5116ADTA
Pin Capacitance (TA = +25°C, VDD, VDDQ = 2.5V ± 0.2V)
Parameter
Input capacitance
Symbol
CI1
CI2
Delta input capacitance
Cdi1
Cdi2
Data input/output capacitance
Delta input/output capacitance
CI/O
Cdio
Pins
CK, /CK
All other input pins
CK, /CK
All other input-only pins
DQ, DM, DQS
DQ, DM, DQS
min.
2.0
2.0
—
—
4.0
—
typ
—
—
—
—
—
—
max.
3.0
3.0
0.25
0.5
5
0.5
Unit
pF
pF
pF
pF
pF
pF
Notes
1
1
1
1
1, 2,
1
Notes: 1. These parameters are measured on conditions:
TA = +25°C.
2. DOUT circuits are disabled.
f = 100MHz, VOUT = VDDQ/2,
∆VOUT
= 0.2V,
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
°
-6B
Parameter
Clock cycle time
(CL = 2)
(CL = 2.5)
CK high-level width
CK low-level width
CK half period
Symbol
tCK
tCK
tCH
tCL
tHP
min.
7.5
6
0.45
0.45
min
(tCH, tCL)
–0.7
max.
12
12
0.55
0.55
—
0.7
0.6
0.45
-7A
min.
7.5
7.5
0.45
0.45
min
(tCH, tCL)
–0.75
–0.75
—
max
12
12
0.55
0.55
—
0.75
0.75
0.5
-7B
min.
10
7.5
0.45
0.45
min
(tCH, tCL)
–0.75
–0.75
—
max.
12
12
0.55
0.55
—
0.75
0.75
0.5
Unit Notes
ns
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
ns
ns
ns
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
8
8
9
8
8
7
5, 11
6, 11
2, 11
2, 11
3
10
DQ output access time from CK, /CK tAC
DQS output access time from CK,
/CK
DQS to DQ skew
tDQSCK –0.6
tDQSQ
—
DQ/DQS output hold time from DQS tQH
Data hold skew factor
Data-out high-impedance time from
CK, /CK
Data-out low-impedance time from
CK, /CK
Read preamble
Read postamble
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input pulse width
Write preamble setup time
Write preamble
Write postamble
tQHS
tHZ
tLZ
tRPRE
tRPST
tDS
tDH
tDIPW
tHP – tQHS —
—
–0.7
–0.7
0.9
0.4
0.45
0.45
1.75
0.55
0.7
0.7
1.1
0.6
—
—
—
—
—
0.6
1.25
—
—
—
tHP – tQHS —
—
–0.75
–0.75
0.9
0.4
0.5
0.5
1.75
0
0.25
0.4
0.75
0.2
0.2
0.35
0.35
0.75
0.75
0.75
1.1
0.6
—
—
—
—
—
0.6
1.25
—
—
—
—
—
—
tHP – tQHS —
—
–0.75
–0.75
0.9
0.4
0.5
0.5
1.75
0
0.25
0.4
0.75
0.2
0.2
0.35
0.35
0.9
0.9
0.75
0.75
0.75
1.1
0.6
—
—
—
—
—
0.6
1.25
—
—
—
—
—
—
tWPRES 0
tWPRE
tWPST
0.25
0.4
0.75
0.2
0.2
0.35
0.35
0.75
0.75
Write command to first DQS latching
tDQSS
transition
DQS falling edge to CK setup time
DQS falling edge hold time from CK
DQS input high pulse width
DQS input low pulse width
tDSS
tDSH
tDQSH
tDQSL
Address and control input setup time tIS
Address and control input hold time
tIH
—
—
0.9
0.9
Data Sheet E0384E30 (Ver. 3.0)
6
ELPIDA [ ELPIDA MEMORY ]
